Patents by Inventor Wei Lim

Wei Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230179216
    Abstract: A multiplexer (MUX) calibration system includes main MUX circuitry, first replica MUX circuitry, digital-to-analog (DAC) circuitry, detection circuitry, and control circuitry. The main MUX circuitry receives clock signals and outputs a first data signal based on the clock signals. The first replica MUX circuitry receives the clock signals and outputs a second data signal based on the clock signals. The DAC circuitry generates an offset voltage. The detection circuitry receives the second data signal and the offset voltage and generates a first error signal based on one or more of the second data signal and the offset voltage. The control circuitry receives the first error signal and generates a first control signal indicating an adjustment to the clock signals.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 8, 2023
    Inventors: Hao-Wei HUNG, Tan Kee HIAN, Siok Wei LIM, Hongtao ZHANG
  • Patent number: 11667771
    Abstract: An elastomeric formulation comprising elastomers, accelerator, antifoaming agent, antioxidant, crosslinker, colouring agent, surfactant, filler, pH adjuster and dispersing medium, wherein the elastomeric formulation has a total solid content ranging between 5% by weight to 40% by weight.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: June 6, 2023
    Assignee: TOP GLOVE INTERNATIONAL SDN. BHD.
    Inventors: Chong Ban Wong, Keuw Wei Lim, Chee Yang Teh, Chun Fah Mok
  • Patent number: 11663154
    Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: May 30, 2023
    Assignee: Intel Corporation
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Publication number: 20230155591
    Abstract: A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one or more power supply rails; a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.
    Type: Application
    Filed: November 16, 2021
    Publication date: May 18, 2023
    Inventors: Nakul NARANG, Siok Wei LIM, Luhui CHEN, Yipeng WANG, Kee Hian TAN
  • Patent number: 11649349
    Abstract: A thermoplastic elastomeric formulation comprises (i) a water based thermoplastic elastomer (TPE), (ii) a surfactant, (iii) an antioxidant, (iv) a antifoaming agent and (v) a crosslinking agent. The water based TPE is styrene-isoprene-styrene (SIS) copolymer latex. A glove that is produced using the thermoplastic elastomeric formulation of the present invention is known as water based TPE gloves, such as water based TPE medical exam gloves, water based TPE household gloves and water based TPE industrial gloves in particular water based TPE surgical gloves.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: May 16, 2023
    Inventors: Chong Ban Wong, Keuw Wei Lim, Arman Sikirman, Chee Kin Phang, Nurjihan Sadon
  • Publication number: 20230127461
    Abstract: A system and method are disclosed for providing a display device with a self-tilting retractable camera mechanism. The retractable camera mechanism includes a display device mounting portion, the display device mounting portion being configured to mechanically attach to a display device; and, a retractable camera mounting portion, the retractable camera mounting portion including a self-tilting mechanism, the self-tilting mechanism causing the retractable camera mounting portion to automatically tilt when the retractable camera mounting portion is in an extended position relative to the display device.
    Type: Application
    Filed: October 27, 2021
    Publication date: April 27, 2023
    Applicant: Dell Products L.P.
    Inventors: Chong Beng Mike Goh, Meng Wei Lim
  • Publication number: 20230100863
    Abstract: Methods and apparatus for processing a substrate area provided herein. For example, methods for enhancing surface hydrophilicity on a substrate comprise a) supplying, using a remote plasma source, water vapor plasma to a processing volume of a plasma processing chamber to treat a bonding surface of the substrate, b) supplying at least one of microwave power or RF power at a frequency from about 1 kHz to 10 GHz and a power from about 1 kW to 10 kW to the plasma processing chamber to maintain the water vapor plasma within the processing volume during operation, and c) continuing a) and b) until the bonding surface of the substrate has a hydrophilic contact angle of less than 10°.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventors: Prayudi LIANTO, Yin Wei LIM, James S. PAPANU, Guan Huei SEE, Eric J. BERGMAN, Nur Yasmeen Addina MOHAMED HELMI ISIK, Wei Ying Doreen YONG, Vicknesh SAHMUGANATHAN, Yi Kun Kelvin GOH, John Leonard SUDIJONO, Arvind SUNDARRAJAN
  • Publication number: 20230026906
    Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.
    Type: Application
    Filed: August 12, 2022
    Publication date: January 26, 2023
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Publication number: 20230017185
    Abstract: A method to determine authenticity of a security feature of an identification document, characterized by receiving a real-time video feed of the identification document with a light source directed at the identification document to make visible a security hologram; processing the real-time video feed into a plurality of image sequence; analysing each image from the plurality of image sequence for a glare and the security hologram, wherein the glare is a reflection of the light source from the identification document; analysing the position of the glare and the security hologram in each image from the plurality of image sequence; evaluating whether the position of the glare and the position of the security hologram is caused by the light source; and providing authenticity result of the identification document captured from the real-time video feed.
    Type: Application
    Filed: September 17, 2021
    Publication date: January 19, 2023
    Applicant: INNOV8TIF SOLUTIONS SDN. BHD.
    Inventors: Yuen Kiat CHEONG, Ken Wei LIM, Calvin YAP, Chin Seong LEE, Seow Joe SEAH, Aaron Patrick NATHANIEL, Tien Soon LAW, Peng Nam SOH, Wei Yan LAU
  • Patent number: 11533170
    Abstract: Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: December 20, 2022
    Assignee: Intel Corporation
    Inventors: Reouven Elbaz, Hooi Kar Loo, Poh Thiam Teoh, Su Wei Lim, Patrick D. Maloney, Santosh Ghosh
  • Publication number: 20220350769
    Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.
    Type: Application
    Filed: April 15, 2022
    Publication date: November 3, 2022
    Applicant: Intel Corporation
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Patent number: 11470897
    Abstract: A semi transparent nitrile glove comprising nitrile latex, caustic alkali, accelerators, vulcanizing agents, stabilizer and antifoaming agent, wherein the nitrile latex is any one selected from either acrylonitrile butadiene copolymer or carboxylated acrylonitrile butadiene copolymer, wherein the caustic alkali is a combination of either potassium hydroxide and ammonia or sodium hydroxide and ammonia, wherein the accelerators are chemical compounds of dithiocarbamates, wherein the vulcanizing agents are selected from both ionic and covalent vulcanizing agents, wherein the stabilizer is any one of either sodium dodecylbenzene sulfonate or sodium dodecyl sulfate and wherein the antifoaming agent is any one from a group consisting of silicone based antifoam, non-silicone based antifoam, oil based antifoam and water based antifoam wherein the semi transparent glove is without pigment and without titanium dioxide.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: October 18, 2022
    Assignee: Top Glove International SDN. BHD.
    Inventors: Chong Ban Wong, Keuw Wei Lim, Kien Ben Liew, Chee Kin Phang
  • Patent number: 11442876
    Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Publication number: 20220156211
    Abstract: Systems or methods of the present disclosure may provide a peripheral component interconnect express (PCIe) device that comprises a programmable fabric. The programmable fabric comprises multiple PCIe physical functions. The programmable fabric also includes switch circuitry having one or more embedded endpoints that dynamically hides or exposes one or more of the multiple PCIe physical functions from a bare metal mode host server without using a reset.
    Type: Application
    Filed: December 22, 2021
    Publication date: May 19, 2022
    Inventors: Eng Hun Ooi, Su Wei Lim, Vaibhav Khamkar
  • Patent number: 11308018
    Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: April 19, 2022
    Assignee: Intel Corporation
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Publication number: 20220116373
    Abstract: An integrated circuit device includes encryption circuitry to encrypt a data packet and scheduler circuitry to receive the encrypted data packet from the encryption circuitry. The scheduler circuitry monitors a duration of time associated with egress of the encrypted data packet, holds the encrypted data packet until the duration of time matches a threshold duration of time, and transmits the encrypted data packet in response to the duration of time matching the threshold duration of time.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Choon Yip Soo, Su Wei Lim, Si Xing Saw, Markos Papadonikolakis
  • Publication number: 20220031627
    Abstract: The present invention provides for a composition, as disclosed herein, for delivery of an active agent. The composition includes a peptide coacervate, wherein the peptide coacervate includes one or more peptides derived from histidine-rich proteins, and an active agent encapsulated in the peptide coacervate. Further provided are a method for encapsulation of an active agent in a peptide coacervate, a method for delivery of an active agent, and a method for treating or diagnosing a condition or disease in a subject in need thereof.
    Type: Application
    Filed: October 20, 2021
    Publication date: February 3, 2022
    Inventors: Ali Gilles Tchenguise MISEREZ, Yuan PING, Zhi Wei LIM, Bartosz Piotr GABRYELCZYK
  • Patent number: 11179342
    Abstract: Described herein is a composition for delivery of an active agent. The composition includes a peptide coacervate, wherein the peptide coacervate includes one or more peptides derived from histidine-rich proteins, and an active agent encapsulated in the peptide coacervate. Further provided are a method for encapsulation of an active agent in a peptide coacervate, a method for delivery of an active agent, and a method for treating or diagnosing a condition or disease in a subject in need thereof.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: November 23, 2021
    Assignee: NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Ali Gilles Tchenguise Miserez, Yuan Ping, Zhi Wei Lim, Bartosz Piotr Gabryelczyk
  • Patent number: 11163717
    Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: November 2, 2021
    Assignee: Intel Corporation
    Inventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
  • Publication number: 20210195897
    Abstract: The present invention relates to an antimicrobial coagulant solution, wherein the antimicrobial coagulant solution is a mixture of an antimicrobial additive and a coagulant solution. The antimicrobial additive formulation comprises (i) natural ingredient, (ii) organic acid and (iii) water. The coagulant solution comprises (i) coagulating agent, (ii) antitack agent, (iii) wetting agent, (iv) pH adjuster and (v) solvent. Further, present invention discloses an antimicrobial elastomeric article comprising antimicrobial coating that is prepared from the antimicrobial coagulant solution. The antimicrobial elastomeric article is an antimicrobial glove.
    Type: Application
    Filed: December 23, 2020
    Publication date: July 1, 2021
    Inventors: CHONG BAN WONG, KEUW WEI LIM, DEVI SHANTINI P.CHANDRASAKARAN