Abstract: A semi transparent nitrile glove comprising nitrile latex, caustic alkali accelerators, vulcanizing agents, stabilizer and antifoaming agent, wherein the nitrile latex is any one selected from either acrylonitrile butadiene copolymer or carboxylated acrylonitrile butadiene copolymer, wherein the caustic alkali is a combination of either potassium hydroxide and ammonia or sodium hydroxide and ammonia, wherein the accelerators are chemical compounds of dithiocarbamates, wherein the vulcanizing agents are selected from both ionic and covalent vulcanizing agents, wherein the stabilizer is any one of either sodium dodecylbenzene sulfonate or sodium dodecyl sulfate and wherein the antifoaming agent is any one from a group consisting of silicone based antifoam, non-silicone based antifoam, oil based antifoam and water based antifoam wherein the semi transparent glove is without pigment and without titanium dioxide.

Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.

Abstract: A thermoplastic elastomeric formulation comprises (i) a water based thermoplastic elastomer (TPE), (ii) a surfactant, (iii) an antioxidant, (iv) a antifoaming agent and (v) a crosslinking agent. The water based TPE is styrene-isoprene-styrene (SIS) copolymer latex. A glove that is produced using the thermoplastic elastomeric formulation of the present invention is known as water based TPE gloves, such as water based TPE medical exam gloves, water based TPE household gloves and water based TPE industrial gloves in particular water based TPE surgical gloves.

Abstract: An elastomeric formulation comprising elastomers, accelerator, antifoaming agent, antioxidant, crosslinker, colouring agent, surfactant, filler, pH adjuster and dispersing medium, wherein the elastomeric formulation has a total solid content ranging between 5% by weight to 40% by weight.

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

Abstract: This document describes a system and method for sharing datasets between various modules or users whereby identity attributes in each dataset are obfuscated. The obfuscation is done such that when the separate datasets are combined, the identity attributes remain obfuscated while the remaining attributes in the combined datasets may be recovered by the users of the invention.

Abstract: An accelerator-free elastomeric formulation comprising base polymers, crosslinkers, stabilizers, an activator, an antioxidant, a pigment, a wax, an antifoam and a pH adjuster. A method of preparing an accelerator-free elastomeric formulation, comprising the steps of mixing Base polymer A with Crosslinker A to produce mixture A, adding while stirring Stabilizer A, Crosslinker B, an activator, an antioxidant, a pigment, a wax and an antifoam one after another with no particular order and followed by a pH adjuster into the mixture A to produce mixture B, adding Base polymer B and Stabilizer B one after another with no particular order into the mixture B to produce an accelerator-free elastomeric formulation and allowing the accelerator-free elastomeric formulation to mature.

Abstract: A latex formulation for making an elastomeric product, more particularly an elastomeric glove. The formulation comprises a mixture of at least one base polymer, a cross-linker; and a pH adjuster, where the pH adjuster provides a pH range of 9.5 to 10.5 to the latex composition. Still further, the present invention discloses a method for preparing a latex formulation for making elastomeric products, such as an elastomeric glove, without using accelerators, zinc oxide or sulphur.

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

Abstract: The present invention provides for a composition, as disclosed herein, for delivery of an active agent. The composition includes a peptide coacervate, wherein the peptide coacervate includes one or more peptides derived from histidine-rich proteins, and an active agent encapsulated in the peptide coacervate. Further provided are a method for encapsulation of an active agent in a peptide coacervate, a method for delivery of an active agent, and a method for treating or diagnosing a condition or disease in a subject in need thereof.

Abstract: A driver circuit includes a driver array configured to generate, at a first output, a multi-bit output signal including a first bit associated with a predetermined first-bit amplitude and a second bit associated with a predetermined second-bit amplitude. The driver array includes first-bit driver slices coupled in parallel between a first input of first data associated with the first bit and the first output, and second-bit driver slices coupled in parallel between a second input of second data associated with the second bit and the first output. A first ratio between a first number of enabled first-bit driver slices and a second number of enabled second-bit driver slices is different from a second ratio between the predetermined first-bit amplitude and the predetermined second-bit amplitude.

Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

Abstract: Apparatus and associated methods relate to a programmable resistor having a resistance iteratively programmed by a calibration control loop. In an illustrative example, the calibration control loop may alternately sample the programmable resistance and a reference resistance by producing a corresponding voltage drop across the resistors. The voltage drops may, for example, be induced by the same constant current source. The calibration control loop may compare the voltage drops with a comparator, for example. In some examples, the comparator may provide a count direction signal to a logic block, generating a calibration code. The calibration code may, for example, be applied to the programmable resistor, such that the resistance of the programmable resistor iteratively approaches the resistance of the reference resistor.

Abstract: Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

Abstract: An apparatus is provided which comprises: an input/output (I/O) port; an adaptor; a physical layer to interface between the I/O port and the adaptor; a first controller associated with a first type of communication; and a second controller associated with a second type of communication, wherein the adaptor is to selectively couple the I/O port, via the physical layer, to one of the first controller or the second controller, based at least in part on a type of device coupled to the I/O port.

Abstract: A latex formulation for making an elastomeric product, more particularly an elastomeric glove. The formulation comprises a mixture of at least one base polymer, a cross-linker; and a pH adjuster, where the pH adjuster provides a pH range of 9.5 to 10.5 to the latex composition. Still further, the present invention discloses a method for preparing a latex formulation for making elastomeric products, such as an elastomeric glove, without using accelerators, zinc oxide or sulphur.