Abstract: A neutron capture therapy system and a target for a particle beam generating device, which may improve the heat dissipation performance of the target, reduce blistering and extend the service life of the target. The neutron capture therapy system includes a neutron generating device and a beam shaping assembly. The neutron generating device includes an accelerator and a target, and a charged particle beam generated by acceleration of the accelerator interacts with the target to generate a neutron beam. The target includes an acting layer, a backing layer and a heat dissipating structure, the acting layer interacts with the charged particle beam to generate the neutron beam, the backing layer supports the action layer, and the heat dissipating structure includes a tubular member composed of tubes arranged side by side.

Abstract: A radiation irradiation system including a radiation generating device and a carrying table, a beam generated by the radiation generating device irradiates an irradiated object on the carrying table, the radiation irradiation system further includes a carrying table positioning device, the carrying table is supported by the carrying table positioning device, the carrying table positioning device includes a positioning mechanism, the positioning mechanism includes a linear axis, the carrying table positioning device may horizontally move along the linear axis, and an extending direction of the linear axis is parallel to an irradiation direction of beams generated by the radiation generating device. In the positioning process of the carrying table, most of the carrying table positioning device is located in the space between the linear axis and the beam outlet, the radioactivity and life-span shortening caused by the radiation of the various components of the carrying table positioning device are reduced.

Abstract: A radiation treatment system and an operation procedure of an irradiation parameter verification device. The radiation treatment system comprises a radiation generation device, an irradiation chamber used for placing a patient, a carrying device used for transferring and bearing the patient, a collimator provided in the irradiation chamber, an irradiation parameter verification device used for determining whether the position of the patient is suitable for performing radiation irradiation treatment or not, and a collimator model, wherein the collimator comprises a collimator outlet; the collimator model comprises a collimator model outlet; the shape and the size of the collimator model outlet are the same as those of the collimator outlet, and the size of the collimator model in the direction perpendicular to the collimator model outlet is smaller than the size of the collimator in the direction perpendicular to the collimator outlet.

Abstract: Methods of forming a metal gate structure of a stacked multi-gate device are provided. A method according to the present disclosure includes depositing a titanium nitride (TiN) layer over a channel region that includes bottom channel layers and top channel layers, depositing a dummy fill layer to cover sidewalls of the bottom channel layers, after the depositing of the dummy fill layer, selectively forming a blocking layer over the TiN layer along sidewalls of the top channel layers, selectively removing the dummy fill layer to release the bottom channel layers, selectively depositing a first work function metal layer to wrap around each of the bottom channel layers, forming a gate isolation layer over a top surface of the first work function metal layer, removing the blocking layer, releasing the top channel layers, and selectively depositing a second work function metal layer to wrap around each of the top channel layers.

Abstract: A signal control method suitable for a touch screen is provided. The signal control method comprises: switching a plurality of scan lines to an enabling voltage level sequentially in a display stage; turning on a plurality of switches sequentially to transmit a plurality of display data to a plurality of data lines when a first scan line of the plurality of scan lines is in an enabled voltage level, wherein a first switch of the plurality of switches is coupled to a first data line of the plurality of data lines, and the first data line corresponds to one of a plurality of dummy lines in a vertical direction, when the first scan line is in the enabled voltage level, the first switch is turned on after other switches are turned on; and setting the plurality of dummy lines to a touch voltage in a touch stage.

Abstract: A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.

Abstract: An image sensor includes a first photodiode and a second photodiode. The image sensor further includes a first color filter over the first photodiode; and a second color filter over the second photodiode. The image sensor further includes a first microlens over the first color filter and a second microlens over the second color filter. The image sensor further includes a first electro-optical (EO) film between the first color filter and the first microlens, wherein a material of the first EO film is configured to change refractive index in response to application of an electrical field. The image sensor further includes a second EO film between the second color filter and the second microlens, wherein a material of the second EO film is configured to change refractive index in response to application of an electrical field.

Abstract: Implementations described herein reduce electron-hole pair generation due to silicon dangling bonds in pixel sensors. In some implementations, the silicon dangling bonds in a pixel sensor may be passivated by silicon-fluorine (Si—F) bonding in various portions of the pixel sensor such as a transfer gate contact via or a shallow trench isolation region, among other examples. The silicon-fluorine bonds are formed by fluorine implantation and/or another type of semiconductor processing operation. In some implementations, the silicon-fluorine bonds are formed as part of a cleaning operation using fluorine (F) such that the fluorine may bond with the silicon of the pixel sensor. Additionally, or alternatively, the silicon-fluorine bonds are formed as part of a doping operation in which boron (B) and/or another p-type doping element is used with fluorine such that the fluorine may bond with the silicon of the pixel sensor.

Abstract: An IC package comprising a substrate with a first vapor chamber; a semiconductor die with a top surface, the semiconductor die stacked over the substrate; wherein the first vapor chamber disposed under the semiconductor die, the first vapor chamber comprises a proximal portion and a distal portion, the proximal portion of the first vapor chamber is thermally coupled to a bottom surface of the semiconductor die; and an encapsulating case encapsulating the semiconductor die and the first vapor chamber, wherein the proximal portion of the first vapor chamber is within the encapsulating case, and the distal portion of the first vapor chamber outside the encapsulating case.

Abstract: A high electron mobility transistor (HEMT) device including the following components is provided. A gate electrode is located on a barrier layer. A source electrode is located on the first side of the gate electrode. A drain electrode is located on the second side of the gate. A source field plate is connected to the source electrode. The source field plate includes first, second, and third field plate portions. The first field plate portion is connected to the source electrode and is located on the first side of the gate electrode. The second field plate portion is located on the second side of the gate electrode. The third field plate portion is connected to the end of the first field plate portion and the end of the second field plate portion. The source field plate has a first opening located directly above the gate electrode.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

Abstract: A neutron capture therapy system is provided, including a neutron generating device and a beam shaping assembly. The neutron capture therapy system further includes a concrete wall forming a space for accommodating the neutron generating device and the beam shaping assembly and shielding radiations generated by the neutron generating device and the beam shaping assembly. A support module is disposed in the concrete wall, the support module is capable of supporting the beam shaping assembly and is used to adjust the position of the beam shaping assembly, and the support module includes concrete and a reinforcing portion at least partially disposed in the concrete. The neutron capture therapy system designs a locally adjustable support for the beam shaping assembly, so that the beam shaping assembly can meet the precision requirement, improve the beam quality, and meet an assembly tolerance of the target.

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a polysilicon structure around the superlattice structure, forming a source/drain opening within the superlattice structure, forming a first conductivity type S/D region within a first portion of the S/D opening, forming an isolation layer on the first conductivity type S/D region and within a second portion of the S/D opening, forming a second conductivity type S/D region on the isolation layer and within a third portion the S/D opening, and replacing the polysilicon structure and the second nanostructured layers with a gate structure that surrounds the first nanostructured layers. Materials of the first and second nanostructured layers are different from each other and the second conductivity type is different from the first conductivity type.

Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

Abstract: The present invention provides a control method of a flash memory controller. By dividing a plurality of logical address to physical address mapping tables into multiple groups, establishing a group-to-physical address mapping table, a storage unit relationship table and a latest updated storage unit table to manage the flash memory controller, the times of loading the group-to-physical address mapping table into a buffer memory can be reduced, so as to improve the efficiency of the flash memory controller.

Abstract: Some implementations described herein include a complementary metal oxide semiconductor image sensor device and techniques to form the complementary metal oxide semiconductor image sensor device. The complementary metal oxide semiconductor image sensor device includes a includes a first array of photodiodes stacked over a second array of photodiodes. A polarization structure is between the first array of photodiodes and the second array of photodiodes. Signaling generated by the first array of photodiodes (e.g., signaling corresponding to unpolarized light waves) may be multiplexed with signaling generated by the second array of photodiodes (e.g., signaling corresponding to polarized light waves). The complementary metal oxide semiconductor image sensor device further includes a filter structure that filters visible light waves and near infrared light waves amongst the first array of photodiodes and the second array of photodiodes.

Abstract: A head-mounted display device includes a main body, a first sensor and a second sensor. The first sensor is disposed on a first setting area of the main body. The second sensor is disposed on a second setting area of the main body. The first setting area and the second setting area respectively have a first central point and a second central point, where the first central point and the second central point are disposed on a horizontal axis. There is a first angle between a connection line of the first central point and the first sensor with the horizontal axis, and there is a second angle between a connection line of the second central point and the second sensor with the horizontal axis, where the first angle is different from the second angle.

Abstract: A method of forming a semiconductor device includes following steps. A first organic layer is formed to cover a first conductive layer. A first opening is formed in the first organic layer to expose a first surface of the first conductive layer. A first silicon layer is formed on a sidewall of the first opening and the first surface of the first conductive layer. A first dielectric layer is formed on the sidewall of the first opening and the first surface of the first conductive layer over the first silicon layer. By using a first mask, portions of the first silicon layer and the first dielectric layer on the first surface are simultaneously removed to expose the first surface, wherein after removing the portions of the first silicon layer and the first dielectric layer, the first dielectric layer covers a top surface of the first silicon layer.

Abstract: The present invention features methods and compositions for the intranasal, sublingual, and subcutaneous administration of bumetanide for the treatment of subjects suffering from edema refractory to oral diuretics.