Abstract: A stand adjustment device has a tripod-connecting member, a connecting seat, a proximal clamping plate, a boom-connecting tube, a locking shaft, and a manual operating member. The connecting seat is rotatably located around the tripod-connecting member. The proximal clamping plate is detachably attached to a side of the connecting seat. One end of the locking shaft is movably disposed in the boom-connecting tube. The boom is slidably mounted through the boom-connecting tube and the locking shaft. The locking shaft is slidably mounted through the boom-connecting tube, the proximal clamping plate, and the connecting seat such that the boom-connecting tube is rotatable relative to the connecting seat. The manual operating member and the locking shaft are configured to clamp the boom-connecting tube, the proximal clamping plate, and the connecting seat therebetween into a locked condition.

Abstract: The disclosure provides a method of active immunotherapy for a cancer patient, comprising administering vaccines against Globo series antigens (i.e., Globo H, SSEA-3 and SSEA-4). Specifically, the method comprises administering Globo H-CRM197 (OBI-833/821) in patients with cancer. The disclosure also provides a method of selecting a cancer patient who is suitable as treatment candidate for immunotherapy. Exemplary immune response can be characterized by reduction of the severity of disease, including but not limited to, prevention of disease, delay in onset of disease, decreased severity of symptoms, decreased morbidity and delayed mortality.

Abstract: A semiconductor device includes a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode. The gate insulating layer is disposed between the gate electrode and the active layer, the source electrode and the drain electrode are arranged on one side of the gate insulating layer, wherein the gate insulating layer includes multilayer oxide films stacked on each other and at least one interface layer between the multilayer oxide films, and the material of the at least one interface layer is different from the material of the oxide films.

Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Abstract: A physical vapor deposition (PVD) system is disclosed. The PVD system includes a pedestal configured to hold a semiconductor wafer, a cover plate configured to hold a target, and a collimator between the pedestal and the cover plate. The collimator includes a plurality of passages configured to pass source material travelling from the cover plate toward the pedestal at an angle less than a threshold angle with respect to a line perpendicular to a surface of the pedestal facing the cover plate, where the collimator is configured to block source material travelling from the cover plate toward the pedestal at an angle greater than the threshold angle, where a first passage of the plurality of passages has a first passage length, where a second passage of the plurality of passages has a second passage length, and where the first passage length is less than the second passage length.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

Abstract: A method for generating and outputting a message is implemented using an electronic device the stores a computer program product and a text database. The text database includes a main message template, a template text that includes a placeholder, and a word group that includes a plurality of preset words for replacing the placeholder. The method includes: in response to receipt of a command for execution of the computer program product, displaying an editing interface including the main message template; in response to receipt of user operation of a selection of the main message template, displaying the template text; in response to receipt of user operation of a selection of one of the preset words via the user interface, generating an edited text by replacing the placeholder with the one of the preset words in the template text; and outputting the edited text as a message.

Abstract: A neutron capture therapy system is provided, including a neutron generating device and a beam shaping assembly. The neutron capture therapy system further includes a concrete wall forming a space for accommodating the neutron generating device and the beam shaping assembly and shielding radiations generated by the neutron generating device and the beam shaping assembly. A support module is disposed in the concrete wall, the support module is capable of supporting the beam shaping assembly and is used to adjust the position of the beam shaping assembly, and the support module includes concrete and a reinforcing portion at least partially disposed in the concrete. The neutron capture therapy system designs a locally adjustable support for the beam shaping assembly, so that the beam shaping assembly can meet the precision requirement, improve the beam quality, and meet an assembly tolerance of the target.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.

Abstract: An information handling system executing an intelligent throughput performance analysis and issue detection system may comprise a network interface device to establish a wireless link with a wireless network and a processor to execute a neural network trained to predict wireless link throughput values based on controlled connectivity testing metrics gathered in a controlled laboratory from tested information handling systems. The processor may gather measured throughput of the wireless link and operational connectivity metrics for the information handling system that describe antenna positional information, antenna adaptation controller parameters, signal strength measurements, and wireless link performance metrics. The neural network may output, based on the gathered operational connectivity metrics a predicted throughput value that differs from the measured throughput by a maximum tolerance.

Abstract: A semiconductor image-sensing structure includes a semiconductor substrate having a front side and a back side, a photo-sensing element disposed in the semiconductor substrate, a color filter disposed over the back side of the semiconductor substrate, and an electric-optical modulator disposed between the color filter and the photo-sensing element. The electric-optical modulator includes a first electrode, a second electrode over the first electrode, and a micro-lens between the first electrode and the second electrode.

Abstract: An optical device includes a substrate, a first electrode, a second electrode, and a first lens. The first electrode and the second electrode are over the substrate and configured to generate a first electric field. The first lens is between the first electrode and the second electrode and has a focal length that varies in response to the first electric field applied to the first lens.

Abstract: An IC package comprises a substrate; a semiconductor die with a top surface, wherein the semiconductor die is stacked over the substrate; a vapor chamber stacked over the semiconductor die, wherein the vapor chamber comprises a proximal portion and a distal portion, the proximal portion covers the top surface of the semiconductor die; and an encapsulating case encapsulating the substrate, the semiconductor die and the vapor chamber, wherein the proximal portion of the vapor chamber is within the encapsulating case, and the distal portion of the vapor chamber extends from a wall of the encapsulating case.

Abstract: A semiconductor image sensing structure includes a semiconductor substrate having a front side and a back side, a pixel sensor disposed in the semiconductor substrate, a transistor disposed over the front side of the semiconductor substrate, and a reflective structure disposed over the front side of the semiconductor substrate. A gate structure of the transistor and the reflective structure include a same material. A top surface of the gate structure of the transistor and a top surface of the reflective structure are aligned with each other.

Abstract: A grid structure in a pixel array may be at least partially angled or tapered toward a top surface of the grid structure such that the width of the grid structure approaches a near-zero width near the top surface of the grid structure. This permits the spacing between color filter regions in between the grid structure to approach a near-zero spacing near the top surfaces of the color filter regions. The tight spacing of color filter regions provided by the angled or tapered grid structure provides a greater surface area and volume for incident light collection in the color filter regions. Moreover, the width of the grid structure may increase at least partially toward a bottom surface of the grid structure such that the wider dimension of the grid structure near the bottom surface of the grid structure provides optical crosstalk protection for the pixel sensors in the pixel array.

Abstract: A pixel sensor may include a main deep trench isolation (DTI) structure and one or more sub-DTI structures in a substrate of the pixel sensor to increase the quantum efficiency of the pixel sensor at large incident angles. The one or more sub-DTI structures may be located within the perimeter of the main DTI structure and above a photodiode. The one or more sub-DTI structures may be configured to provide a path of travel for incident light into the photodiode from large incident angles in that the one or more sub-DTI structures may be filled with an oxide material to increase light penetration into the one or more sub-DTI structures. This may reduce reflections at a top surface of the substrate, thereby permitting incident light to refract into the substrate and toward the photodiode.

Abstract: A pixel sensor may include a layer stack to reduce and/or block the effects of plasma and etching on a photodiode and/or other lower-level layers. The layer stack may include a first oxide layer, a layer having a band gap that is approximately less than 8.8 electron-Volts (eV), and a second oxide layer. The layer stack may reduce and/or prevent the penetration and absorption of ultraviolet photons resulting from the plasma and etching processes, which may otherwise cause the formation of electron-hole pairs in the substrate in which the photodiode is included.