Patents by Inventor Wei-Lin Chen

Wei-Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220262892
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation element over the magnetic element. The i magnetic element is wider than the isolation element. The semiconductor device structure further includes a conductive line over the isolation element.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Yu KU, Chi-Cheng CHEN, Hon-Lin HUANG, Wei-Li HUANG, Chun-Yi WU, Chen-Shien CHEN
  • Patent number: 11417643
    Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Chin-Liang Chen, Jing Ruei Lu
  • Publication number: 20220254799
    Abstract: A semiconductor device is provided. The semiconductor device includes a first vertical stack, a first vertical channel line, a first data storage structure, and a first gate dielectric structure. The first vertical stack includes a first conductive line and a second conductive line. The first vertical channel line vertically passes through the first conductive line and the second conductive line, and the first vertical channel line is a P-type channel. The first data storage structure is disposed between the first conductive line and the first vertical channel line. The first gate dielectric structure is disposed between the second conductive line and the first vertical channel line.
    Type: Application
    Filed: October 7, 2021
    Publication date: August 11, 2022
    Inventors: Hang-Ting LUE, Cheng-Lin SUNG, Wei-Chen CHEN
  • Patent number: 11411107
    Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Jen Lai, Yen-Ming Chen, Tsung-Lin Lee
  • Publication number: 20220247433
    Abstract: Disclosed herein are related to systems and methods for correcting non-linearity due to duty cycle error. In one aspect, a system includes a mixer configured to up-convert transmission (Tx) data, a coefficient calibrator configured to select a target value of a coefficient based on a measurement of an interference signal due to non-linearity of the mixer, and an interference canceller coupled to the coefficient calibrator and the mixer. In some embodiments, the interference canceller is configured to generate compensated Tx data based on the Tx data and the selected target value of the coefficient and provide the compensated Tx data to the mixer. In some embodiments, the compensated Tx data corrects for the non-linearity of the mixer.
    Type: Application
    Filed: March 19, 2021
    Publication date: August 4, 2022
    Inventors: Bevin George Perumana, Mohyee Mikhemar, Tirdad Sowlati, Alvin Lin, Sudharshan Srinivasan, Wei-Hong Chen
  • Publication number: 20220247435
    Abstract: Disclosed herein are related to systems and methods for selectively disabling current steering circuitries. In one aspect, the system includes a balun including a first inductor and a second inductor, a first current steering circuit coupled to the first inductor, a second current steering circuit coupled to the first inductor, and a controller coupled to the first current steering circuit and the second current steering circuit. In one aspect, the controller is configured to, based on input data having a first state, apply a first signal and a second signal having a first level to the first current steering circuit and a third signal and a fourth signal having the first level to the second current steering circuit to disable a first current through the second inductor, a second current through the first current steering circuit, and a third current through the second current steering circuit.
    Type: Application
    Filed: March 19, 2021
    Publication date: August 4, 2022
    Inventors: Bevin George Perumana, Mohyee Mikhemar, Tirdad Sowlati, Alvin Lin, Sudharshan Srinivasan, Wei-Hong Chen
  • Publication number: 20220246513
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first under-bump metallization (UBM) pattern, a first conductive via, and a first dielectric layer laterally covering the first UBM pattern and the first conductive via. Entireties of a top surface and a bottom surface of the first UBM pattern are substantially planar. The first conductive via landing on the top surface of the first UBM pattern includes a vertical sidewall and a top surface connected to the vertical sidewall, and a planarized mark is on the top surface of the first conductive via. A bottom surface of the first dielectric layer is substantially flush with the bottom surface of the first UBM, and a top surface of the first dielectric layer is substantially flush with the top surface of the first conductive via.
    Type: Application
    Filed: April 20, 2022
    Publication date: August 4, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Jiun-Yi Wu, Chi-Yang Yu, Yu-Min Liang, Wei-Yu Chen
  • Publication number: 20220239331
    Abstract: Various novel concepts and schemes pertaining to non-orthogonal multiple access for wireless communications are described. A group orthogonal coded access (GOCA) scheme is introduced to reduce multi-user interference (MUI) and improve performance. A repetition division multiple access (RDMA) scheme is introduced to differentiate user equipment (UEs) by different repetition patterns. A low-density spreading (LDS) scheme is introduced to reduce MUI and improve performance.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Guo-Hau Gau, Ho-Chi Huang, Wei-Jen Chen, Chiou-Wei Tsai, Ju-Ya Chen, Mau-Lin Wu
  • Patent number: 11398844
    Abstract: Disclosed herein are related to systems and methods for selectively disabling current steering circuitries. In one aspect, the system includes a balun including a first inductor and a second inductor, a first current steering circuit coupled to the first inductor, a second current steering circuit coupled to the first inductor, and a controller coupled to the first current steering circuit and the second current steering circuit. In one aspect, the controller is configured to, based on input data having a first state, apply a first signal and a second signal having a first level to the first current steering circuit and a third signal and a fourth signal having the first level to the second current steering circuit to disable a first current through the second inductor, a second current through the first current steering circuit, and a third current through the second current steering circuit.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: July 26, 2022
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Bevin George Perumana, Mohyee Mikhemar, Tirdad Sowlati, Alvin Lin, Sudharshan Srinivasan, Wei-Hong Chen
  • Patent number: 11392743
    Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
  • Patent number: 11387168
    Abstract: A semiconductor device includes a first conductive layer, an organic layer and a silicon layer. The first conductive layer includes a first surface. The organic layer is disposed over the first surface of the first conductive layer. The silicon layer is disposed over the organic layer and extended onto and in contact with the first surface of the first conductive layer.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
  • Publication number: 20220216351
    Abstract: A method for manufacturing a sensing device is provided. The method includes: providing a substrate; forming a sensing unit on the substrate; forming a first light-shielding layer on the sensing unit; forming a first anti-reflection layer on the sensing unit; and patterning the first light-shielding layer and the first anti-reflection layer using a single lithography process to form a first pinhole corresponding to the sensing unit.
    Type: Application
    Filed: December 8, 2021
    Publication date: July 7, 2022
    Inventors: Wei-Lin WAN, Yu-Tsung LIU, Ming-Chih CHEN, Te-Yu LEE
  • Patent number: 11380777
    Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: July 5, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee, Tai-Ju Chen
  • Publication number: 20220209989
    Abstract: Example methods and computer systems for packet handling for active-active stateful service insertion are disclosed. One example may involve in response to detecting a first packet from a first active logical service router (SR), a computer system generating and storing state information that associates (a) the first active logical SR and (b) first tuple information specified by the first packet. The first active logical SR and a second active logical SR may be both associated with the service endpoint address and configured to operate in an active-active mode. In response to detecting the second packet from a destination responsive to the first packet, the computer system may select the first active logical SR over the second active logical SR based on the state information and second tuple information specified by the second packet; and send the second packet towards the first active logical SR for processing according to a stateful service.
    Type: Application
    Filed: August 25, 2020
    Publication date: June 30, 2022
    Applicant: VMware, Inc.
    Inventors: Bo LIN, Dong Ping CHEN, Wei WANG, Yi ZENG, Xinyu HE, Dahui YUAN, Xiao LIANG
  • Publication number: 20220208684
    Abstract: An interface of integrated circuit (IC) die includes a plurality of the contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and divided into a transmitting group and a receiving group. The contact elements of the transmitting group have a first contact element sequence and the contact elements of the receiving group have a second contact element sequence, the first contact element sequence is identical to the second contact element sequence. The contact elements with the first contact element sequence and the second contact element sequence are matched when the contact element pattern is geometrically rotated by 180° with respect to a row direction and a column direction.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Hao Wang, Ting-Chin Cho, Igor Elkanovich, Amnon Parnass, Chia-Hsiang Chang, Tsai-Ming Yang, Yen-Chung T. Chen, Ting-Hsu Chien, Yuan-Hung Lin, Chao-Ching Huang, Li-Ya Tseng, Pei Yu, Jia-Liang Chen, Yen-Wei Chen, Chung-Kai Wang, Chun-Hsu Chen, Yu-Ju Chang, Li-Hua Lin, Zanyu Yang
  • Publication number: 20220145496
    Abstract: A process produces a thermoplastic polyurethane (TPU) fiber with low shrinkage, in particular at a high spinning speed. The resulting fiber can be used for fabric, especially for garments and shoes. The process combines the high-speed spinning process with the heat-setting process. This allows the process to produce a TPU fiber in high productivity, which could greatly decrease the cost. Moreover, the obtained TPU fiber has very low shrinkage of <10%, which makes it well suitable as the main raw material in fabrics.
    Type: Application
    Filed: February 11, 2020
    Publication date: May 12, 2022
    Applicants: BASF SE, Haining Xin Gao Fibres Ltd
    Inventors: De Hui YIN, Wei Zhuang, Hui Zhi YAN, Wei Lin Chen, Gendi Gan, Lizhong Zhu, Shengjie Zou
  • Publication number: 20220088416
    Abstract: A neutron capture therapy system and a target for a particle beam generating device, which may improve the heat dissipation performance of the target, reduce blistering and extend the service life of the target. The neutron capture therapy system includes a neutron generating device and a beam shaping assembly. The neutron generating device includes an accelerator and a target, and a charg\ed particle beam generated by acceleration of the accelerator interacts with the target to generate a neutron beam. The target includes an acting layer, a backing layer and a heat dissipating structure, the acting layer interacts with the charged particle beam to generate the neutron beam, the backing layer supports the action layer, and the heat dissipating structure includes a tubular member composed of tubes arranged side by side.
    Type: Application
    Filed: December 1, 2021
    Publication date: March 24, 2022
    Inventors: Yuan-Hao Liu, Wei-Lin Chen
  • Publication number: 20220080225
    Abstract: A neutron capture therapy system may prevent deformation and damage of a material of a beam shaping assembly (20), thereby improving flux and quality of a neutron source. A boron neutron capture therapy system (100) includes a neutron generating device (10) and a beam shaping assembly (20), where the neutron generating device (10) includes an accelerator (11) and a target (T), a charged particle beam (P) generated by acceleration of the accelerator (11) interacts with the target (T) to generate neutrons, the neutrons form a neutron beam (N), the neutron beam (N) defines a main axis (X); the beam shaping assembly (20) includes a moderator (231), a reflector (232), and a radiation shield (233); and the beam shaping assembly (20) further includes a frame (21) accommodating the moderator (231).
    Type: Application
    Filed: October 6, 2021
    Publication date: March 17, 2022
    Inventors: Wei-Lin CHEN, Tao Jiang
  • Publication number: 20220080224
    Abstract: A neutron capture therapy system is provided, which may prevent a material of a beam shaping assembly from deformation and damaged, and improve the flux and quality of neutron sources. A boron neutron capture therapy system (100) includes a neutron generating device (10) and a beam shaping assembly (20). The neutron generating device (10) includes an accelerator (11) and a target (T). A charged particle beam (P) generated by acceleration of the accelerator (11) acts with the target (T) to generate neutrons. The neutrons form a neutron beam (N). The neutron beam (N) defines a main axis (X). The beam shaping assembly (20) includes a support part (21) and a main part (23) filled within the support part (21).
    Type: Application
    Filed: October 6, 2021
    Publication date: March 17, 2022
    Inventors: Wei-Lin CHEN, Tao Jiang, Fa-Zhi Yan
  • Patent number: 11224766
    Abstract: A neutron capture therapy system and a target for a particle beam generating device, which may improve the heat dissipation performance of the target, reduce blistering and extend the service life of the target. The neutron capture therapy system includes a neutron generating device and a beam shaping assembly. The neutron generating device includes an accelerator and a target, and a charged particle beam generated by acceleration of the accelerator interacts with the target to generate a neutron beam. The target includes an acting layer, a backing layer and a heat dissipating layer, the acting layer interacts with the charged particle beam to generate the neutron beam, the base layer supports the action layer, and the heat dissipating layer includes a tubular member composed of tubes arranged side by side.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: January 18, 2022
    Assignee: NEUBORON MEDTECH LTD.
    Inventors: Yuan-Hao Liu, Wei-Lin Chen