Patents by Inventor Wei-Ming Wang
Wei-Ming Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128178Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.Type: ApplicationFiled: February 8, 2023Publication date: April 18, 2024Inventors: Yu-Hung LIN, Wei-Ming WANG, Su-Chun YANG, Jih-Churng TWU, Shih-Peng TAI, Kuo-Chung YEE
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Publication number: 20240113034Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.Type: ApplicationFiled: February 8, 2023Publication date: April 4, 2024Inventors: Yu-Hung LIN, Wei-Ming WANG, Chih-Hao YU, PaoTai HUANG, Pei-Hsuan LO, Shih-Peng TAI
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Publication number: 20240096830Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.Type: ApplicationFiled: January 9, 2023Publication date: March 21, 2024Inventors: Yu-Yi Huang, Yu-Hung Lin, Wei-Ming Wang, Chen Chen, Shih-Peng Tai, Kuo-Chung Yee
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Publication number: 20240079239Abstract: A method includes implanting impurities in a semiconductor substrate to form an etch stop region within the semiconductor substrate; forming a transistor structure on a front side of the semiconductor substrate; forming a front-side interconnect structure over the transistor structure; performing a thinning process on a back side of the semiconductor substrate to reduce a thickness of the semiconductor substrate, wherein the thinning process is slowed by the etch stop region; and forming a back-side interconnect structure over the back side of the semiconductor substrate.Type: ApplicationFiled: January 10, 2023Publication date: March 7, 2024Inventors: Bau-Ming Wang, Liang-Yin Chen, Wei Tse Hsu, Jung-Tsan Tsai, Ya-Ching Tseng, Chunyii Liu
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Patent number: 11913472Abstract: A centrifugal heat dissipation fan including a housing and an impeller disposed in the housing on an axis is provided. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions. A heat dissipation system of an electronic device is also provided.Type: GrantFiled: April 6, 2021Date of Patent: February 27, 2024Assignee: Acer IncorporatedInventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
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Patent number: 11916155Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.Type: GrantFiled: May 21, 2021Date of Patent: February 27, 2024Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATIONInventors: Chien-Hsiu Huang, Bo-Jhih Chen, Kuo-Ming Chiu, Meng-Sung Chou, Wei-Te Cheng, Kai-Chieh Liang, Yun-Ta Chen, Yu-Han Wang
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Publication number: 20240047216Abstract: A method includes forming an etching mask over a first wafer. The etching mask covers an inner portion of the first wafer. A wafer edge trimming process is performed to trim an edge portion of the first wafer, with the etching mask protecting the inner portion of the first wafer from being etched. The edge portion forms a full ring encircling the inner portion of the first wafer. The method further includes removing the etching mask, and bonding the first wafer to a second wafer.Type: ApplicationFiled: August 2, 2022Publication date: February 8, 2024Inventors: Wei-Ming Wang, Yu-Hung Lin, Shih-Peng Tai, Kuo-Chung Yee
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Publication number: 20240014091Abstract: A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.Type: ApplicationFiled: July 11, 2022Publication date: January 11, 2024Inventors: Wei-Ming Wang, Yu-Hung Lin, Shih-Peng Tai, Kuo-Chung Yee
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Publication number: 20230402340Abstract: A semiconductor device including a first semiconductor die, a second semiconductor die, thermal silicon substrates and an encapsulation is provided. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The thermal silicon substrates are disposed on the first semiconductor die, wherein the thermal silicon substrates are spaced apart from the second semiconductor die. The encapsulation is disposed on the first semiconductor die. The encapsulation encapsulates the second semiconductor die and the thermal silicon substrates. The encapsulation includes a filling material layer and an insulator, wherein the filling material layer is disposed on the first semiconductor die and located between the second semiconductor die and thermal silicon substrates, and the filling material layer is spaced apart from the second semiconductor die and the thermal silicon substrates by the insulator.Type: ApplicationFiled: May 18, 2022Publication date: December 14, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Lin, Shih-Peng Tai, Kuo-Chung Yee, Chen-Hua Yu, Wei-Ming Wang
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Publication number: 20230397512Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.Type: ApplicationFiled: August 10, 2023Publication date: December 7, 2023Inventors: Huei-Tsz WANG, Po-Shu WANG, Wei-Ming WANG
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Publication number: 20230386961Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor die, a semiconductor frame structure, a semiconductor cover structure and conductive balls. The substrate has a ground plate embedded therein. The semiconductor die is disposed on the substrate and electrically connected with the substrate. The semiconductor frame structure is disposed on the substrate and surrounds the semiconductor die. The semiconductor frame structure includes conductive through semiconductor vias (TSVs) penetrating through the semiconductor frame structure, and at least one conductive TSV is electrically connected with the ground plate. The semiconductor cover structure is disposed on the semiconductor frame structure and on the semiconductor die. The semiconductor cover structure includes a conductive grid pattern and the conductive grid pattern contacts the conductive TSVs.Type: ApplicationFiled: May 30, 2022Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Ming Wang, Yu-Hung Lin, Shih-Peng Tai
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Publication number: 20230386806Abstract: A system and method for reducing particle contamination on substrates during a deposition process using a particle control system is disclosed here. In one embodiment, a film deposition system includes: a processing chamber sealable to create a pressurized environment and configured to contain a plasma, a target and a substrate in the pressurized environment; and a particle control unit, wherein the particle control unit is configured to provide an external force to each of at least one charged atom and at least one contamination particle in the plasma, wherein the at least one charged atom and the at last one contamination particle are generated by the target when it is in direct contact with the plasma, wherein the external force is configured to direct the at least one charged atom to a top surface of the substrate and to direct the at least one contamination particle away from the top surface of the substrate.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Inventors: Tsung-Han Kuo, Po-Shu Wang, Wei-Ming Wang
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Publication number: 20230366081Abstract: Some implementations described herein provide techniques and apparatuses for determining a performance of a dry-clean operation within a deposition tool. A cleaning-control subsystem of the deposition tool may include a gas concentration sensor and a temperature sensor mounted in an exhaust system of the deposition tool to monitor the dry-clean operation. The gas concentration sensor may provide data related to a concentration of a chemical compound in a cleaning gas, where the chemical compound is a bi-product of the dry-clean operation. The temperature sensor may provide temperature data related to an exothermic reaction of the dry-clean operation. Such data may be used to determine an efficiency and/or an effectiveness of the dry-clean operation within the deposition tool.Type: ApplicationFiled: May 11, 2022Publication date: November 16, 2023Inventors: Ker-hsun LIAO, Wei-Ming WANG, Yen-Hsing CHEN, Lun-Kuang TAN, Yi Chen HO
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Patent number: 11818970Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.Type: GrantFiled: August 4, 2022Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huei-Tsz Wang, Po-Shu Wang, Wei-Ming Wang
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Publication number: 20230361048Abstract: A semiconductor package includes a substrate, a first die, a second die, a resistant layer, an encapsulant and an interlink structure. The first die has a first thickness larger than a second thickness of the second die. The resistant layer is disposed on the first and second dies and conformally covers the first and second dies. The encapsulant is disposed on the resistant layer and wraps around the first and second dies. The interlink structure is disposed above the first and second dies and embedded in the encapsulant, and the interlink structure is electrically connected with the first and second dies. The interlink structure includes a first via portion vertically extending through the encapsulant and connected to the first die, a second via portion extending vertically through the encapsulant and connected to the second die, and a routing line portion disposed on and connected with the first and second via portions, and the first via portion is shorter than the second via portion.Type: ApplicationFiled: May 5, 2022Publication date: November 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Ming Wang, Yu-Hung Lin, Shih-Peng Tai, Kuo-Chung Yee
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Publication number: 20230358412Abstract: There is provided an auto detection system including a thermal detection device and a host. The host controls an indication device to indicate a prompt message or detection results according to a slope variation of voltage values or 2D distribution of temperature values detected by the thermal detection device, wherein the voltage values include the detected voltage of a single pixel or the sum of detected voltages of multiple pixels of a thermal sensor.Type: ApplicationFiled: July 20, 2023Publication date: November 9, 2023Inventors: CHIH-MING SUN, MING-HAN TSAI, CHIUNG-WEN LIN, PO-WEI YU, WEI-MING WANG, SEN-HUANG HUANG
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Publication number: 20230343677Abstract: A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, a semiconductor substrate disposed on the dielectric layer and including a via opening with a notch in proximity to the dielectric layer, a through substrate via (TSV) disposed in the via opening of the semiconductor substrate and extending into the dielectric layer to land on the conductive pad, and a dielectric liner disposed in the via opening of the semiconductor substrate and filling the notch to laterally separate the TSV from the semiconductor substrate. A surface of the dielectric liner facing the TSV is substantially leveled with an inner sidewall of the dielectric layer facing the TSV.Type: ApplicationFiled: April 25, 2022Publication date: October 26, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Ming Wang, Yu-Hung Lin, Yu-Hsiao Lin, Shih-Peng Tai, Kuo-Chung Yee
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Publication number: 20230343559Abstract: Some implementations described herein provide techniques and apparatuses for overcoming forces that may deflect an injector nozzle into an interior wall of a thin-film furnace. The implementations include a fixture that is coupled to the injector nozzle. The fixture is configurable to lock to a selected property of the injector nozzle to maintain, between a portion of the injector nozzle and the interior wall, a gap. In this way, the portion of the injector nozzle is prevented from colliding with the interior wall and dislodging particulates that may contaminate semiconductor product fabricated using the thin-film furnace.Type: ApplicationFiled: April 21, 2022Publication date: October 26, 2023Inventors: Yi Chen HO, Chih Ping LIAO, Shih Hao YANG, Wei-Ming WANG, Chien Ting LIN, Jie-Ying YANG, Chih-Che TANG, Kuo Kang TENG, Ming-Hui YU, Ker-hsun LIAO, Chi-Hsun LIN
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Patent number: 11776796Abstract: A system and method for reducing particle contamination on substrates during a deposition process using a particle control system is disclosed here. In one embodiment, a film deposition system includes: a processing chamber sealable to create a pressurized environment and configured to contain a plasma, a target and a substrate in the pressurized environment; and a particle control unit, wherein the particle control unit is configured to provide an external force to each of at least one charged atom and at least one contamination particle in the plasma, wherein the at least one charged atom and the at last one contamination particle are generated by the target when it is in direct contact with the plasma, wherein the external force is configured to direct the at least one charged atom to a top surface of the substrate and to direct the at least one contamination particle away from the top surface of the substrate.Type: GrantFiled: June 30, 2021Date of Patent: October 3, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Han Kuo, Po-Shu Wang, Wei-Ming Wang
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Publication number: 20230287952Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.Type: ApplicationFiled: March 10, 2022Publication date: September 14, 2023Inventors: Yi Chen HO, Chih Ping LIAO, Chien Ting LIN, Jie-Ying YANG, Wei-Ming WANG, Ker-Hsun LIAO, Chi-Hsun LIN