Patents by Inventor Wei-Ming Wang

Wei-Ming Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113034
    Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.
    Type: Application
    Filed: February 8, 2023
    Publication date: April 4, 2024
    Inventors: Yu-Hung LIN, Wei-Ming WANG, Chih-Hao YU, PaoTai HUANG, Pei-Hsuan LO, Shih-Peng TAI
  • Publication number: 20240096830
    Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Yi Huang, Yu-Hung Lin, Wei-Ming Wang, Chen Chen, Shih-Peng Tai, Kuo-Chung Yee
  • Publication number: 20240047216
    Abstract: A method includes forming an etching mask over a first wafer. The etching mask covers an inner portion of the first wafer. A wafer edge trimming process is performed to trim an edge portion of the first wafer, with the etching mask protecting the inner portion of the first wafer from being etched. The edge portion forms a full ring encircling the inner portion of the first wafer. The method further includes removing the etching mask, and bonding the first wafer to a second wafer.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 8, 2024
    Inventors: Wei-Ming Wang, Yu-Hung Lin, Shih-Peng Tai, Kuo-Chung Yee
  • Publication number: 20240014091
    Abstract: A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.
    Type: Application
    Filed: July 11, 2022
    Publication date: January 11, 2024
    Inventors: Wei-Ming Wang, Yu-Hung Lin, Shih-Peng Tai, Kuo-Chung Yee
  • Publication number: 20230402340
    Abstract: A semiconductor device including a first semiconductor die, a second semiconductor die, thermal silicon substrates and an encapsulation is provided. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The thermal silicon substrates are disposed on the first semiconductor die, wherein the thermal silicon substrates are spaced apart from the second semiconductor die. The encapsulation is disposed on the first semiconductor die. The encapsulation encapsulates the second semiconductor die and the thermal silicon substrates. The encapsulation includes a filling material layer and an insulator, wherein the filling material layer is disposed on the first semiconductor die and located between the second semiconductor die and thermal silicon substrates, and the filling material layer is spaced apart from the second semiconductor die and the thermal silicon substrates by the insulator.
    Type: Application
    Filed: May 18, 2022
    Publication date: December 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Shih-Peng Tai, Kuo-Chung Yee, Chen-Hua Yu, Wei-Ming Wang
  • Publication number: 20230397512
    Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 7, 2023
    Inventors: Huei-Tsz WANG, Po-Shu WANG, Wei-Ming WANG
  • Publication number: 20230386961
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor die, a semiconductor frame structure, a semiconductor cover structure and conductive balls. The substrate has a ground plate embedded therein. The semiconductor die is disposed on the substrate and electrically connected with the substrate. The semiconductor frame structure is disposed on the substrate and surrounds the semiconductor die. The semiconductor frame structure includes conductive through semiconductor vias (TSVs) penetrating through the semiconductor frame structure, and at least one conductive TSV is electrically connected with the ground plate. The semiconductor cover structure is disposed on the semiconductor frame structure and on the semiconductor die. The semiconductor cover structure includes a conductive grid pattern and the conductive grid pattern contacts the conductive TSVs.
    Type: Application
    Filed: May 30, 2022
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ming Wang, Yu-Hung Lin, Shih-Peng Tai
  • Publication number: 20230386806
    Abstract: A system and method for reducing particle contamination on substrates during a deposition process using a particle control system is disclosed here. In one embodiment, a film deposition system includes: a processing chamber sealable to create a pressurized environment and configured to contain a plasma, a target and a substrate in the pressurized environment; and a particle control unit, wherein the particle control unit is configured to provide an external force to each of at least one charged atom and at least one contamination particle in the plasma, wherein the at least one charged atom and the at last one contamination particle are generated by the target when it is in direct contact with the plasma, wherein the external force is configured to direct the at least one charged atom to a top surface of the substrate and to direct the at least one contamination particle away from the top surface of the substrate.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Inventors: Tsung-Han Kuo, Po-Shu Wang, Wei-Ming Wang
  • Publication number: 20230366081
    Abstract: Some implementations described herein provide techniques and apparatuses for determining a performance of a dry-clean operation within a deposition tool. A cleaning-control subsystem of the deposition tool may include a gas concentration sensor and a temperature sensor mounted in an exhaust system of the deposition tool to monitor the dry-clean operation. The gas concentration sensor may provide data related to a concentration of a chemical compound in a cleaning gas, where the chemical compound is a bi-product of the dry-clean operation. The temperature sensor may provide temperature data related to an exothermic reaction of the dry-clean operation. Such data may be used to determine an efficiency and/or an effectiveness of the dry-clean operation within the deposition tool.
    Type: Application
    Filed: May 11, 2022
    Publication date: November 16, 2023
    Inventors: Ker-hsun LIAO, Wei-Ming WANG, Yen-Hsing CHEN, Lun-Kuang TAN, Yi Chen HO
  • Patent number: 11818970
    Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huei-Tsz Wang, Po-Shu Wang, Wei-Ming Wang
  • Publication number: 20230361048
    Abstract: A semiconductor package includes a substrate, a first die, a second die, a resistant layer, an encapsulant and an interlink structure. The first die has a first thickness larger than a second thickness of the second die. The resistant layer is disposed on the first and second dies and conformally covers the first and second dies. The encapsulant is disposed on the resistant layer and wraps around the first and second dies. The interlink structure is disposed above the first and second dies and embedded in the encapsulant, and the interlink structure is electrically connected with the first and second dies. The interlink structure includes a first via portion vertically extending through the encapsulant and connected to the first die, a second via portion extending vertically through the encapsulant and connected to the second die, and a routing line portion disposed on and connected with the first and second via portions, and the first via portion is shorter than the second via portion.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ming Wang, Yu-Hung Lin, Shih-Peng Tai, Kuo-Chung Yee
  • Publication number: 20230358412
    Abstract: There is provided an auto detection system including a thermal detection device and a host. The host controls an indication device to indicate a prompt message or detection results according to a slope variation of voltage values or 2D distribution of temperature values detected by the thermal detection device, wherein the voltage values include the detected voltage of a single pixel or the sum of detected voltages of multiple pixels of a thermal sensor.
    Type: Application
    Filed: July 20, 2023
    Publication date: November 9, 2023
    Inventors: CHIH-MING SUN, MING-HAN TSAI, CHIUNG-WEN LIN, PO-WEI YU, WEI-MING WANG, SEN-HUANG HUANG
  • Publication number: 20230343677
    Abstract: A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, a semiconductor substrate disposed on the dielectric layer and including a via opening with a notch in proximity to the dielectric layer, a through substrate via (TSV) disposed in the via opening of the semiconductor substrate and extending into the dielectric layer to land on the conductive pad, and a dielectric liner disposed in the via opening of the semiconductor substrate and filling the notch to laterally separate the TSV from the semiconductor substrate. A surface of the dielectric liner facing the TSV is substantially leveled with an inner sidewall of the dielectric layer facing the TSV.
    Type: Application
    Filed: April 25, 2022
    Publication date: October 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ming Wang, Yu-Hung Lin, Yu-Hsiao Lin, Shih-Peng Tai, Kuo-Chung Yee
  • Publication number: 20230343559
    Abstract: Some implementations described herein provide techniques and apparatuses for overcoming forces that may deflect an injector nozzle into an interior wall of a thin-film furnace. The implementations include a fixture that is coupled to the injector nozzle. The fixture is configurable to lock to a selected property of the injector nozzle to maintain, between a portion of the injector nozzle and the interior wall, a gap. In this way, the portion of the injector nozzle is prevented from colliding with the interior wall and dislodging particulates that may contaminate semiconductor product fabricated using the thin-film furnace.
    Type: Application
    Filed: April 21, 2022
    Publication date: October 26, 2023
    Inventors: Yi Chen HO, Chih Ping LIAO, Shih Hao YANG, Wei-Ming WANG, Chien Ting LIN, Jie-Ying YANG, Chih-Che TANG, Kuo Kang TENG, Ming-Hui YU, Ker-hsun LIAO, Chi-Hsun LIN
  • Patent number: 11776796
    Abstract: A system and method for reducing particle contamination on substrates during a deposition process using a particle control system is disclosed here. In one embodiment, a film deposition system includes: a processing chamber sealable to create a pressurized environment and configured to contain a plasma, a target and a substrate in the pressurized environment; and a particle control unit, wherein the particle control unit is configured to provide an external force to each of at least one charged atom and at least one contamination particle in the plasma, wherein the at least one charged atom and the at last one contamination particle are generated by the target when it is in direct contact with the plasma, wherein the external force is configured to direct the at least one charged atom to a top surface of the substrate and to direct the at least one contamination particle away from the top surface of the substrate.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Kuo, Po-Shu Wang, Wei-Ming Wang
  • Publication number: 20230287952
    Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Inventors: Yi Chen HO, Chih Ping LIAO, Chien Ting LIN, Jie-Ying YANG, Wei-Ming WANG, Ker-Hsun LIAO, Chi-Hsun LIN
  • Patent number: 11754293
    Abstract: There is provided an auto detection system including a thermal detection device and a host. The host controls an indication device to indicate a prompt message or detection results according to a slope variation of voltage values or 2D distribution of temperature values detected by the thermal detection device, wherein the voltage values include the detected voltage of a single pixel or the sum of detected voltages of multiple pixels of a thermal sensor.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: September 12, 2023
    Assignee: PIXART IMAGING INC.
    Inventors: Chih-Ming Sun, Ming-Han Tsai, Chiung-Wen Lin, Po-Wei Yu, Wei-Ming Wang, Sen-Huang Huang
  • Publication number: 20230207409
    Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.
    Type: Application
    Filed: March 1, 2023
    Publication date: June 29, 2023
    Inventors: Sheng-Chieh CHEN, Wei-Ming Wang, Ming-Lun Lee, Chih-Ren Hsieh, Ming Chyi Liu
  • Patent number: 11678592
    Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: June 13, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ming Wang, Chia-Wei Liu, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao, Huei-Tzu Wang
  • Patent number: 11637046
    Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Chieh Chen, Chih-Ren Hsieh, Ming-Lun Lee, Wei-Ming Wang, Ming Chyi Liu