Patents by Inventor Wei-Ming Wang
Wei-Ming Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11776796Abstract: A system and method for reducing particle contamination on substrates during a deposition process using a particle control system is disclosed here. In one embodiment, a film deposition system includes: a processing chamber sealable to create a pressurized environment and configured to contain a plasma, a target and a substrate in the pressurized environment; and a particle control unit, wherein the particle control unit is configured to provide an external force to each of at least one charged atom and at least one contamination particle in the plasma, wherein the at least one charged atom and the at last one contamination particle are generated by the target when it is in direct contact with the plasma, wherein the external force is configured to direct the at least one charged atom to a top surface of the substrate and to direct the at least one contamination particle away from the top surface of the substrate.Type: GrantFiled: June 30, 2021Date of Patent: October 3, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Han Kuo, Po-Shu Wang, Wei-Ming Wang
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Publication number: 20230287952Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.Type: ApplicationFiled: March 10, 2022Publication date: September 14, 2023Inventors: Yi Chen HO, Chih Ping LIAO, Chien Ting LIN, Jie-Ying YANG, Wei-Ming WANG, Ker-Hsun LIAO, Chi-Hsun LIN
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Patent number: 11754293Abstract: There is provided an auto detection system including a thermal detection device and a host. The host controls an indication device to indicate a prompt message or detection results according to a slope variation of voltage values or 2D distribution of temperature values detected by the thermal detection device, wherein the voltage values include the detected voltage of a single pixel or the sum of detected voltages of multiple pixels of a thermal sensor.Type: GrantFiled: January 26, 2022Date of Patent: September 12, 2023Assignee: PIXART IMAGING INC.Inventors: Chih-Ming Sun, Ming-Han Tsai, Chiung-Wen Lin, Po-Wei Yu, Wei-Ming Wang, Sen-Huang Huang
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Publication number: 20230207409Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.Type: ApplicationFiled: March 1, 2023Publication date: June 29, 2023Inventors: Sheng-Chieh CHEN, Wei-Ming Wang, Ming-Lun Lee, Chih-Ren Hsieh, Ming Chyi Liu
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Patent number: 11678592Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.Type: GrantFiled: May 25, 2021Date of Patent: June 13, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Ming Wang, Chia-Wei Liu, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao, Huei-Tzu Wang
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Patent number: 11637046Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.Type: GrantFiled: September 14, 2021Date of Patent: April 25, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Chieh Chen, Chih-Ren Hsieh, Ming-Lun Lee, Wei-Ming Wang, Ming Chyi Liu
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Patent number: 11600543Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.Type: GrantFiled: September 14, 2021Date of Patent: March 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Chieh Chen, Chih-Ren Hsieh, Ming-Lun Lee, Wei-Ming Wang, Ming Chyi Liu
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Publication number: 20220376175Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.Type: ApplicationFiled: August 4, 2022Publication date: November 24, 2022Inventors: Huei-Tsz WANG, Po-Shu Wang, Wei-Ming Wang
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Patent number: 11430953Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.Type: GrantFiled: January 4, 2021Date of Patent: August 30, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huei-Tsz Wang, Po-Shu Wang, Wei-Ming Wang
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Publication number: 20220270943Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.Type: ApplicationFiled: September 14, 2021Publication date: August 25, 2022Inventors: Sheng-Chieh CHEN, Chih-Ren HSIEH, Ming-Lun LEE, Wei-Ming WANG, Ming Chyi LIU
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Publication number: 20220146115Abstract: There is provided an auto detection system including a thermal detection device and a host. The host controls an indication device to indicate a prompt message or detection results according to a slope variation of voltage values or 2D distribution of temperature values detected by the thermal detection device, wherein the voltage values include the detected voltage of a single pixel or the sum of detected voltages of multiple pixels of a thermal sensor.Type: ApplicationFiled: January 26, 2022Publication date: May 12, 2022Inventors: CHIH-MING SUN, MING-HAN TSAI, CHIUNG-WEN LIN, PO-WEI YU, WEI-MING WANG, SEN-HUANG HUANG
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Patent number: 11280500Abstract: There is provided an auto detection system including a thermal detection device and a host. The host controls an indication device to indicate a prompt message or detection results according to a slope variation of voltage values or 2D distribution of temperature values detected by the thermal detection device, wherein the voltage values include the detected voltage of a single pixel or the sum of detected voltages of multiple pixels of a thermal sensor.Type: GrantFiled: March 13, 2020Date of Patent: March 22, 2022Assignee: PIXART IMAGING INC.Inventors: Chih-Ming Sun, Ming-Han Tsai, Chiung-Wen Lin, Po-Wei Yu, Wei-Ming Wang, Sen-Huang Huang
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Publication number: 20210327693Abstract: A system and method for reducing particle contamination on substrates during a deposition process using a particle control system is disclosed here. In one embodiment, a film deposition system includes: a processing chamber sealable to create a pressurized environment and configured to contain a plasma, a target and a substrate in the pressurized environment; and a particle control unit, wherein the particle control unit is configured to provide an external force to each of at least one charged atom and at least one contamination particle in the plasma, wherein the at least one charged atom and the at last one contamination particle are generated by the target when it is in direct contact with the plasma, wherein the external force is configured to direct the at least one charged atom to a top surface of the substrate and to direct the at least one contamination particle away from the top surface of the substrate.Type: ApplicationFiled: June 30, 2021Publication date: October 21, 2021Inventors: Tsung-Han KUO, Po-Shu WANG, Wei-Ming WANG
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Publication number: 20210280783Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.Type: ApplicationFiled: May 25, 2021Publication date: September 9, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Ming Wang, Chia-Wei Liu, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao, Huei-Tzu Wang
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Patent number: 11056324Abstract: A system and method for reducing particle contamination on substrates during a deposition process using a particle control system is disclosed here. In one embodiment, a film deposition system includes: a processing chamber sealable to create a pressurized environment and configured to contain a plasma, a target and a substrate in the pressurized environment; and a particle control unit, wherein the particle control unit is configured to provide an external force to each of at least one charged atom and at least one contamination particle in the plasma, wherein the at least one charged atom and the at last one contamination particle are generated by the target when it is in direct contact with the plasma, wherein the external force is configured to direct the at least one charged atom to a top surface of the substrate and to direct the at least one contamination particle away from the top surface of the substrate.Type: GrantFiled: August 2, 2019Date of Patent: July 6, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Han Kuo, Po-Shu Wang, Wei-Ming Wang
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Patent number: 11038108Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.Type: GrantFiled: May 24, 2019Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Ming Wang, Chia-Wei Liu, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao, Huei-Tzu Wang
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Publication number: 20210135103Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.Type: ApplicationFiled: January 4, 2021Publication date: May 6, 2021Inventors: Huei-Tsz WANG, Po-Shu Wang, Wei-Ming Wang
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Patent number: 10886465Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.Type: GrantFiled: February 28, 2018Date of Patent: January 5, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huei-Tsz Wang, Po-Shu Wang, Wei-Ming Wang
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Publication number: 20200373487Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.Type: ApplicationFiled: May 24, 2019Publication date: November 26, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Ming Wang, Chia-Wei Liu, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao, Huei-Tzu Wang
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Publication number: 20200224886Abstract: There is provided an auto detection system including a thermal detection device and a host. The host controls an indication device to indicate a prompt message or detection results according to a slope variation of voltage values or 2D distribution of temperature values detected by the thermal detection device, wherein the voltage values include the detected voltage of a single pixel or the sum of detected voltages of multiple pixels of a thermal sensor.Type: ApplicationFiled: March 13, 2020Publication date: July 16, 2020Inventors: Chih-Ming SUN, Ming-Han TSAI, Chiung-Wen LIN, Po-Wei YU, Wei-Ming WANG, Sen-Huang HUANG