Abstract: An integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. The integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. The first active device has an output coupled to a first layer deep line that is in the low resistivity portion. The second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. The low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.

Abstract: A monolithic three-dimensional (3D) integrated circuit (IC) device includes a lower tier including a lower tier cell and an upper tier arranged over the lower tier. The upper tier has a first upper tier cell and a second upper tier cell separated by a predetermined lateral space. A monolithic inter-tier via (MIV) extends from the lower tier through the predetermined lateral space, and the MIV has a first end electrically connected to the lower tier cell and a second end electrically connected to the first upper tier cell.

Abstract: An integrated circuit includes a horizontal routing track in a first metal layer, and a backside routing track in a backside metal layer. The backside metal layer and the first metal layer are formed at opposite sides of a semiconductor substrate. The horizontal routing track is conductively connected to a first terminal of a first transistor without passing through a routing track in another metal layer. The backside routing track is conductively connected to a second terminal of the first transistor without passing through a routing track in another metal layer.

Abstract: A method is provided, including following operations: identifying a first contact via, a second contact via, or a combination thereof in a first standard cell, wherein the first contact via is coupled between a first active region and a first conductive line on a first side, and the second contact via is coupled between a second active region and a second conductive line on a second side; calculating a first cell height according to a first width of the first and second active regions, and calculating a second cell height according to a second width of the first and second active regions; calculating multiple first available cell heights based on a ratio between the first and second cell heights; generating layout designs of multiple first cells; and manufacturing at least first one element in the integrated circuit based on the layout designs of the first cells.

Abstract: A method includes patterning a substrate to define a semiconductor strip over the substrate; and forming a backside via adjacent to the semiconductor strip. The method further includes depositing a dielectric material. The method further includes etching the dielectric material to define an isolation structure having a top surface lower than a top surface of the semiconductor strip. The method further includes forming a source/drain structure over the semiconductor strip. The method further includes forming an interlayer dielectric layer over the source/drain structure. The method further includes etching the interlayer dielectric layer and the isolation structure to define an opening exposing the backside via. The method further includes forming a source/drain contact in the opening.

Abstract: Certain triazole compounds have good LPAR1 antagonistic activity and selectivity, low toxicity, and good metabolic stability, and can be used for preventing or treating the LPAR1-related disease or disorder. The IC50 value of some triazole compounds can be below 300 nM, even 50 nM. The range of CC50 of the triazole compounds can be greater than 200 ?M. They also show good metabolic stability in human, fancy rats, and house mice.

Abstract: Certain compounds are lysophosphatidic acid receptor antagonists have high LPAR1 antagonist activity and selectivity, low toxicity, good metabolic stability, promising pharmaceutical development prospects, and may be used for preventing or treating LPAR1-related diseases or illnesses. The IC50 values of some of the compounds may be as low as 300 nM or below, even 50 nM or below. In addition, CC50 value range of the compounds may be as high as 200 ?M or above. Furthermore, the compounds have good metabolic stability in humans, mice and rats.

Abstract: An epidermal biosensor comprising a diffusion layer operable to dissolve a solid-phase epidermal analyte, an enzymatic bioreceptor operable to oxidise the dissolved epidermal analyte from the diffusion layer, a transducer having an interface with the diffusion layer, a processor configured to process electrochemical data from the transducer, and a substrate to which the enzymatic bioreceptor and the transducer are attached. The solid-phase epidermal analyte may include water-insoluble cholesterol and water-soluble lactate. The diffusion-solvation layer may comprise agarose hydrogel and additives including glycerol and/or gelatin to improve mechanical robustness and reduce water evaporation rate of the hydrogel, and ethanol and/or Triton X-100 to facilitate solvation and transportation of hydrophobic analytes.

Abstract: A flip-flop device includes first through third power rails, a first plurality of conductive patterns positioned at a total of three locations evenly spaced between the first and second power rails, a second plurality of conductive patterns positioned at a total of three locations evenly spaced between the second and third power rails, a master latching circuit including a first subset of each of the first and second pluralities of conductive patterns, a slave latching circuit including a second subset of each of the first and second pluralities of conductive patterns, and a gate conductor extending across at least one of the three locations of the first plurality of conductive patterns and at least one of the three locations of the second plurality of conductive patterns. The gate conductor is configured to transmit one of a first clock signal or a feedback signal of the flip-flop device.

Abstract: An integrated circuit (IC) package includes a first die including first IC devices electrically connected to a first signal routing structure positioned at a first surface and a second surface opposite the first surface, wherein the first die has a first orientation of the first and second surfaces along a first direction, a second die comprising including second IC devices electrically connected to a second signal routing structure positioned at a third surface and a fourth surface opposite the first surface, wherein the second die has a second orientation of the third and fourth surfaces along the first direction opposite the first orientation, and a power distribution structure extending between the second and fourth surfaces and electrically connected to each of the first and second IC devices.

Abstract: An integrated circuit includes frontside power rails in a frontside metal layer above the substrate, backside signal lines in a first backside metal layer below the substrate, backside power rails in a second backside metal layer below the first backside metal layer, and backside via-connectors passing through the substrate. A first frontside power rail and a first backside via-connector are conductively connected to the source terminal of a first-type transistor. A second frontside power rail and a second backside via-connector are conductively connected to the source terminal of a second-type transistor. A first extended via-connector is directly connected between the first backside via-connector and a first backside power rail. A second extended via-connector is directly connected between the second backside via-connector and a second backside power rail.

Abstract: A method of manufacturing a semiconductor device, including: providing a substrate including a first cell and a second cell; forming a plurality of first metal strips on a first plane; forming a first trench over a boundary between the first cell and the second cell, wherein a bottom surface of the first trench is located on a second plane over the first plane; filling the first trench with a non-conductive material, resulting in a separating wall; and forming a plurality of second metal strips on a third plane over the second plane, wherein the plurality of second metal strips comprise a first second metal strip and a second second metal strip separated from each other by the separating wall.

Abstract: The present disclosure discloses a quantitative evaluation system and evaluation method for hemangioma. The evaluation system includes an image acquisition module, an image analysis module, a result evaluation module and a display module. The image acquisition module includes a light source device, an imaging device and a storage device. The image analysis module includes a digital signal processor and digital analysis software. The digital signal processor divides pixel points of the hemangioma image into a tumor image and a tumor side image. The digital analysis software calculates comprehensive red, green, blue (RGB) values of the tumor image and the tumor side image. The result evaluation module includes a therapeutic evaluation coefficient, and the therapeutic evaluation coefficient=tumor comprehensive RGB value-tumor-side comprehensive RGB value.

Abstract: A light-emitting diode (LED) includes a transmissible substrate, an epitaxial layered structure, a distributed Bragg reflector (DBR) structure, a first electrode, and a second electrode. The epitaxial layered structure is disposed on the transmissible substrate. The DBR structure is disposed on the epitaxial layered structure opposite to the transmissible substrate. The DBR structure has at least one first through hole and at least one second through hole, and is formed with a plurality of voids. The first electrode and the second electrode are electrically connected to the first semiconductor layer and the second semiconductor layer, respectively. An LED packaged module including the LED is also disclosed.

Abstract: A method may include accessing a dataset including multiple data subsets, each of the data subsets corresponding to a feature of the dataset. Data in the data subsets may be analyzed to determine a characteristic of the data. In addition, a prompt template may be selected from prompt templates for the one of the data subsets based on the determined characteristic of the data. Prompts may be generated using the prompt template and the data from the one of the data subsets. The prompts may be provided to an LLM. The prompts may command the LLM to perform one or more operations with respect to the data of the one of the data subsets. One or more additional data subsets may be created for the dataset based on response of the LLM. Each of the one or more additional data subsets may correspond to a new feature of the dataset.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first conductivity type arranged in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second conductivity type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line arranged in a third layer between the first layer and the second layer. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate includes a recess portion, wherein the first conductive line is at an elevation of the recess portion.

Abstract: According to an aspect of an embodiment, one or more operations may include accessing a dataset including multiple data subsets. Feature type candidates corresponding to the data subsets may be identified. The one or more operations may further include building first machine learning models using different sets of feature type candidates. Each of the different sets of feature type candidates may be scored based on respective accuracies, relative to the dataset, of each first machine learning model that respectively corresponds to each different set of feature type candidates. A final set of feature types may be selected from the different sets of feature type candidates based on the scores of the different sets of feature types. The operations may further include training a second machine learning model using a labeled dataset that is generated by applying the final set of feature types to the dataset.

Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

Abstract: An ear canal clamp for small animals includes a base and a clamping mechanism. The clamping mechanism includes two clamping arms movably mounted on the base, a biasing member mounted on the base and constrained between the clamping arms, and two ear canal positioning members mounted respectively to the clamping arms and facing each other. The clamping arms are configured to move toward each other and compress the biasing member to increase the distance between the ear canal positioning members. A biasing force generated by the biasing member when compressed is used to push the clamping arms to move oppositely with respect to each other.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a first cell, a dielectric layer, and a snorkel structure. The first cell has an output terminal. The dielectric layer is disposed on the first cell. The snorkel structure is disposed in the dielectric layer. The snorkel structure includes a first conductive structure, a first conductive layer, and a second conductive structure. The first conductive layer is electrically connected to the output terminal of the cell. The first conductive layer is disposed on and electrically connected to the first conductive structure. The second conductive structure is disposed on and electrically connected to the first conductive layer. The second conductive structure has a topmost conductive layer buried in the dielectric layer.