Patents by Inventor Wei Peng

Wei Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240104288
    Abstract: A system for manufacturing an integrated circuit includes a processor coupled to a non-transitory computer readable medium configured to store executable instructions. The processor is configured to execute the instructions for generating a layout design of the integrated circuit that has a set of design rules. The generating of the layout design includes generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and generating a first via layout pattern corresponding to a first via. The cut feature layout pattern overlaps a first gate layout pattern of the set of gate layout patterns.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Inventors: Shih-Wei PENG, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Shun Li CHEN, Wei-Cheng LIN
  • Publication number: 20240103097
    Abstract: The present disclosure provides a direct current (DC) transformer error detection apparatus for a pulsating harmonic signal, including a DC and pulsating harmonic current output module and an external detected input module, where the DC and pulsating harmonic current output module outputs a DC and a DC superimposed pulsating harmonic current to an internal sampling circuit and a self-calibrated standard resistor array; and the internal sampling circuit converts the input DC and the input DC superimposed pulsating harmonic current into a voltage signal, and sends the voltage signal to an analog-to-digital (AD) sampling and measurement component through a front-end conditioning circuit and a detected input channel. The DC transformer error detection apparatus can complete self-calibration for measurement of the DC and the pulsating harmonic signal on a test site.
    Type: Application
    Filed: August 17, 2022
    Publication date: March 28, 2024
    Inventors: Xin Zheng, Wenjing Yu, Tao Peng, Yi Fang, Ming Lei, Hong Shi, Ben Ma, Li Ding, Wei Wei, Linghua Li, He Yu, Tian Xia, Yingchun Wang, Sike Wang, Dongri Xie, Xin Wang, Bo Pang, Xianjin Rong
  • Publication number: 20240105091
    Abstract: The present disclosure provides a gate driving circuit, a method of driving a gate driving circuit, and a display panel. The gate driving circuit includes a plurality of driving units connected in cascade. Each driving unit includes: N shift register units; and a mode control circuit connected to the N shift register units, wherein the mode control circuit is configured to receive a control signal for the driving unit, and connect the N shift register units in one of a plurality of resolution modes under the control of the control signal.
    Type: Application
    Filed: October 20, 2023
    Publication date: March 28, 2024
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Weixing Liu, Wei Qin, Kuanjun Peng, Tieshi Wang, Chunfang Zhang, Hui Zhang, Changfeng Li, Shunhang Zhang, Kai Hou, Hongrun Wang, Liwei Liu, Yunsik Im, Wanpeng Teng, Xiaolong Li, Kai Guo, Zhiqiang Xu
  • Publication number: 20240103328
    Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.
    Type: Application
    Filed: June 29, 2021
    Publication date: March 28, 2024
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Zhen Zhang, Fuqiang Li, Zhenyu Zhang, Yunping Di, Lizhong Wang, Zheng Fang, Jiahui Han, Yawei Wang, Chenyang Zhang, Chengfu Xu, Ce Ning, Pengxia Liang, Feihu Zhou, Xianqin Meng, Weiting Peng, Qiuli Wang, Binbin Tong, Rui Huang, Tianmin Zhou, Wei Yang
  • Publication number: 20240100546
    Abstract: Coarse particle flotation equipment and method based on coupled fluidization of cyclone and damping are provided. The flotation equipment includes a flotation column. A raw ore feed pipe is provided in an upper part of the flotation column. The flotation column is sequentially divided into a mine tailing bottom launder area, a cyclone mineralization area and a static separation area from bottom to top. A plurality of water-gas mixing jet pipes which are obliquely arranged inwardly and upwardly and communicated with an inner cavity of the flotation column being provided at a side wall of the cyclone mineralization area, jet directions of the plurality of water-gas mixing jet pipes are distributed clockwise or anticlockwise around an axis of the flotation column, and a damping element for reducing turbulence of a water flow is further provided between the cyclone mineralization area and the static separation area.
    Type: Application
    Filed: November 8, 2021
    Publication date: March 28, 2024
    Applicant: CENTRAL SOUTH UNIVERSITY
    Inventors: Wei SUN, Haisheng HAN, Jian PENG, Yao XIAO, Yuehua HU
  • Patent number: 11941318
    Abstract: The present application provides an audio and video playing system, a playing method and a playing device. The system comprises: a display device; a directional sound output module configured to output a directional sound signal; a tracking element configured to monitor a target visual area and to monitor the target display area on the display screen; and a processor, connected with the directional sound output module and the tracking element respectively, and configured to acquire a first audio and video data to be output in the target display area, display image information of the first audio and video data in the target display area, and output sound information of the first audio and video data to the directional sound output module such that the directional sound output module output a directional sound signal towards the target visual area.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 26, 2024
    Assignees: Beijing BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xiaomang Zhang, Xiangjun Peng, Tiankuo Shi, Chenxi Zhao, Shuo Zhang, Yifan Hou, Yan Sun, Li Tian, Jing Liu, Wei Sun, Zhihua Ji, Yanhui Xi
  • Patent number: 11942470
    Abstract: A semiconductor device includes a first cell. The first cell is surrounded by a castle-shaped forbidden region. The first cell includes a first active region, a second active region, and at least one via. The first active region and the second active region extend along a first direction and are separated from each other along a second direction traverse to the first direction. The first active region partially overlaps an upper region of the castle-shaped forbidden region, and the second active region partially overlaps a lower region of the castle-shaped forbidden region. The at least one via is arranged outside the castle-shaped forbidden region.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng
  • Publication number: 20240091764
    Abstract: A combinable nucleic acid pre-processing apparatus includes a sample transfer chamber transferring a sample from a sampling tube to a nucleic acid extraction kit, a nucleic acid extraction chamber performing a nucleic acid extraction of the sample in the nucleic acid extraction kit for obtaining a nucleic acid extract, an assay setup chamber preparing reagents and transferring reagents and the nucleic acid extract to an assay plate, and at least two bridging modules respectively disposed between the sample transfer chamber and the nucleic acid extraction chamber and between the nucleic acid extraction chamber and the assay setup chamber. The sample transfer chamber, the nucleic acid extraction chamber and the assay setup chamber are separated and operated independently. Three chambers are connected through the bridging modules, so the nucleic acid extraction kit can be sequentially moved in the sample transfer chamber, the nucleic acid extraction chamber and the assay setup chamber.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 21, 2024
    Inventors: Chien-Ting Liu, Shih-Fang Peng, Song-Bin Huang, Guo-Wei Huang, Jen-Chih Tsai
  • Publication number: 20240096884
    Abstract: A method of making a semiconductor device includes forming a first polysilicon structure over a first portion of a substrate. The method further includes forming a first spacer on a sidewall of the first polysilicon structure, wherein the first spacer has a concave corner region between an upper portion and a lower portion. The method further includes forming a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, and a difference between the first thickness and the second thickness is at most 10% of the second thickness.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Shao CHENG, Chui-Ya PENG, Kung-Wei LEE, Shin-Yeu TSAI
  • Publication number: 20240094538
    Abstract: The present disclosure provides a near-eye display device and a construction method for a meta lens. The near-eye display device includes a substrate (10), a meta lens array (40) provided on the side of the substrate (10) close to an eye (100), and a pixel island array (30) located on the side of the substrate (10) away from the eye (100). The pixel island array (30) includes a plurality of pixel islands. The meta lens array (40) includes a plurality of meta lenses. The orthographic projection of the lens center of the meta lens on the substrate (10) overlaps the orthographic projection of the pixel center of the pixel island on the substrate. The lens center is the geometric center of the meta lens, and the pixel center is the geometric center of the pixel island.
    Type: Application
    Filed: December 27, 2021
    Publication date: March 21, 2024
    Inventors: Weiting PENG, Qiuyu LING, Wei WANG, Xianqin MENG, Pengxia LIANG, Qian WU
  • Publication number: 20240095072
    Abstract: A method includes, in response to receiving an incoming service request and establishing a call chain of pods of a service mesh network, setting a retry locker parameter to a locked state for each pod in the call chain. A locked retry locker parameter prevents the pod from initiating retries of a service request. The method includes, in response to determining that a pod in the call chain is unavailable, setting the retry locker parameter to an unlocked state for a previous pod just prior to the pod that is unavailable. The unlocked state allows a retry to the pod that is unavailable. In response to the previous pod reaching a retry limit, the method includes setting the retry locker parameter to unlocked for each pod in the call chain and sending a service termination message to a service requester.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 21, 2024
    Inventors: Yue Wang, Wei Wu, Xin Peng Liu, Liang Wang, Biao Chai
  • Publication number: 20240096830
    Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Yi Huang, Yu-Hung Lin, Wei-Ming Wang, Chen Chen, Shih-Peng Tai, Kuo-Chung Yee
  • Publication number: 20240096805
    Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Inventors: Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng
  • Publication number: 20240096867
    Abstract: A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Charles Chew-Yuen YOUNG, Chih-Liang CHEN, Chih-Ming LAI, Jiann-Tyng TZENG, Shun-Li CHEN, Kam-Tou SIO, Shih-Wei PENG, Chun-Kuang CHEN, Ru-Gun LIU
  • Patent number: 11935830
    Abstract: An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Hsin Chiu, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng, Jiun-Wei Lu
  • Publication number: 20240088019
    Abstract: A connecting structure includes a first dielectric layer, a first connecting via in the first dielectric layer, a second connecting via in the first dielectric layer, and an isolation between the first connecting via and the second connecting via. The isolation separates the first and second connecting vias from each other. The first connecting via, the isolation and the second connecting via are line symmetrical about a central line perpendicular to a top surface of the first dielectric layer.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 14, 2024
    Inventors: CHIA CHEN LEE, CHIA-TIEN WU, SHIH-WEI PENG, KUAN YU CHEN
  • Patent number: 11929363
    Abstract: In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Li-Wei Chu, Ming-Fu Tsai, Jam-Wem Lee, Yu-Ti Su
  • Patent number: 11926852
    Abstract: The present invention relates to compositions comprising polypeptides having xylanase activity and polypeptides having arabinofuranosidase activity for use in, e.g., animal feed. The present invention further relates to polypeptides having arabinofuranosidase activity, polypeptides having xylanase activity and polynucleotides encoding the polypeptides. The invention also relates to nucleic acid constructs, vectors, and host cells comprising the polynucleotides as well as methods of producing and using the polypeptides.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: March 12, 2024
    Assignee: Novozymes A/S
    Inventors: Wei Peng, Ninfa Rangel Pedersen, Dan Pettersson, Jens Magnus Eklof, Soren Nymand-Grarup, Lorena G. Palmen, Rune Nygaard Monrad, Nikolaj Spodsberg, Mary Ann Stringer, Charlotte Blom, Lars Kiemer, Kristian Bertel Romer M. Krogh, Jesper Salomon
  • Patent number: 11922879
    Abstract: A display substrate and a display device. The display substrate includes a pixel circuit in which the driving circuit controls a driving current for driving the light emitter element to emit light; the first light emission control circuit applies a first voltage to a first terminal of the driving circuit in response to a first light emission control signal; the second light emission control circuit applies the driving current to the light emitter element in response to a second light emission control signal; the first reset circuit applies a first reset voltage to the control terminal of the driving circuit in response to a first reset signal; the first reset signal and the first light emission control signal are simultaneously turn-on signals during a period; the first light emission control line and the second light emission control line extend along a first direction and are arranged in a second direction.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: March 5, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xueling Gao, Kuanjun Peng, Chengchung Yang, Xiangxiang Zou, Wei Qin
  • Patent number: 11923273
    Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of first metal strips extending in a first direction on a first plane; and forming a plurality of second metal strips extending in the first direction on a second plane over the first plane by executing a photolithography operation with a single mask, wherein a first second metal strip (FIG. 1, 131) is disposed over a first first metal strip; wherein the first first metal strip and the first second metal strip are directed to a first voltage source; wherein a distance between the first second metal strip and a second second metal strip immediate adjacent to the first second metal strip is greater than a distance between the second second metal strip and a third second metal strip immediate adjacent to the second second metal strip.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Wei Peng, Chia-Tien Wu, Jiann-Tyng Tzeng