Abstract: A light-emitting device includes a semiconductor laminate, a first contact electrode, and a second contact electrode. The semiconductor laminate includes a first semiconductor layer, an active layer, and a second semiconductor layer being laminated in a thickness direction. The semiconductor laminate has a first portion having a patterned structure that has a first surface constituted by the first semiconductor layer, a second surface opposite to the first surface and away from the first semiconductor layer, and a side surface interconnecting the first surface and the second surface, and a second portion being a light-emitting area. The first contact electrode is formed on the first portion, electrically connected to the first semiconductor layer and in contact with the first surface, the second surface and the side surface of the patterned structure. The second contact electrode is formed on the second portion and electrically connected to the second semiconductor layer.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating video anchors for a video. In one aspect, a method includes obtaining key moment identifiers for a video, where each key moment identifier includes a time index value specifying a playback time in the video, and is indicative subject matter of the video that has been determined to meet one or more interest criteria that define salient topics within the video. For each key moment identifier, a video anchor is generated, where each video anchor indicates a playback time for the video, and may include an image of a frame that occurs near the playback time. Upon a selection of the video anchor by the user, an instruction in the video anchor causes a video player to begin playback of the video at the playback time specified by the video anchor.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first type in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line in a third layer between the first and second layers. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate includes an upper portion and a lower portion, and the first conductive line crosses the first gate between the upper portion and the lower portion.

Abstract: A multi-channel pipetting assembly includes a linkage member and a plurality of pipetting structures arranged in parallel. Each pipetting structure includes a pipette body, a piston rod, a piston tube, and an elastic element. The pipette body has a plurality of air chambers with different inner diameters, and the air chambers are arranged axially and communicate with each other. The piston rod is fixed to the linkage member. The piston tube is sleeved on the piston rod. The piston rod and the piston tube are located in the pipette body, and are axially and reciprocatingly movable in the pipette body. The piston rod matches the air chamber with the smallest inner diameter, and the piston tube matches the remaining air chambers. The elastic element is telescopically sleeved on the piston rod and corresponds to the piston tube. Therefore, a plurality of volume ranges meeting the accuracy requirements can be provided.

Abstract: An integrated circuit includes a first conductive structure including a root portion of the first conductive structure, tine portions that are arranged in a first semiconductor layer, a neck portion surrounded by a film structure. The integrated circuit further includes a second conductive structure having first and second portions that are stacked along a first direction. The first portion of the second conductive structure is surrounded by the film structure and the second portion of the second conductive structure is in the first semiconductor layer. A third conductive structure in the integrated circuit has horizontal and vertical structures. The horizontal structure extends in a second semiconductor layer and the vertical structure passes through the second semiconductor layer and the film structure to contact a first conductive rail. The first conductive rail and the tine portions are apart from the horizontal structure along the first direction by a same distance.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first conductive pattern disposed within a first region from a top view perspective and extending along a first direction, a first phase shift circuit disposed within the first region, a first transmission circuit disposed within a second region from the top view perspective, and a first gate conductor extending from the first region to the second region along a second direction perpendicular to the first direction. The first phase shift circuit and the first transmission circuit are electrically connected with the first conductive pattern through the first gate conductor.

Abstract: According to an aspect of an embodiment, operations include receiving a set of NL descriptors and a corresponding set of PL codes. The operations further include determining a first vector associated with each NL descriptor and a second vector associated with each PL code, using language models. The operations further include determining a number of a set of semantic code classes to cluster the set of PL codes into the set of semantic code classes, based on the number, the first vector, and the second vector. The operations further include training a multi-class classifier model to predict a semantic code class, from the set of semantic code classes, corresponding to an input NL descriptor. The operations further include selecting an intra-class predictor model based on the predicted semantic code class. The operations further include training the intra-class predictor model to predict a PL code corresponding to the input NL descriptor.

Abstract: A semiconductor device includes first and second conductive layers, a first epitaxial structure and a first via structure. The first conductive layer extends along a first direction, and provides a first reference voltage signal. The second conductive layer extends along the first direction, and is separated from the first conductive layer along a second direction. The first epitaxial structure is disposed between the first conductive layer and the second conductive layer, and has a first width along the first direction. The first via structure is disposed between the first conductive layer and the second conductive layer, and transmits the first reference voltage signal from the first conductive layer through the second conductive layer to the first epitaxial structure. The first via structure has a second width along the first direction. The second width is approximately equal to or larger than twice of the first width.

Abstract: A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

Abstract: A light-emitting diode includes a substrate, a distributed Bragg reflector (DBR) structure and a semiconductor layered structure. The DBR structure is disposed on the substrate. The semiconductor layered structure is disposed on the DBR structure opposite to the substrate, and is configured to emit a light having a first wavelength. The DBR structure has a reflectance of not greater than 30% for the light having the first wavelength, and a reflectance of not smaller than 50% for a laser beam having a second wavelength that is different from the first wavelength.

Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

Abstract: An integrated circuit includes a plurality of first layer deep lines and a plurality of first layer shallow lines. The integrated circuit also includes a plurality of second layer deep lines and a plurality of second layer shallow lines. Each of the first layer deep lines and the first layer shallow lines is in a first conductive layer. Each of the second layer deep lines and the second layer shallow lines is in a second conductive layer above the first conductive layer.

Abstract: One aspect of this description relates to an integrated circuit. In some aspects, the integrated circuit includes a first pattern metal layer, a second pattern metal layer disposed over the first pattern metal layer, wherein the second pattern metal layer includes a second plurality of metal tracks extending in a first direction, and a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer including a first metal track segment and a second metal track segment shifted in a second direction from the first metal track segment, wherein the second plurality of metal tracks, and at least a portion of each of the first metal track segment and the second metal track segment are within a double cell height in the second direction.

Abstract: A method of forming an integrated circuit (IC) package includes constructing a first power distribution structure on a first die included in the IC package, thereby electrically connecting the first power distribution structure to a second power distribution structure positioned on a back side of the first die, and bonding a third power distribution structure to the first power distribution structure, the third power distribution structure being positioned on a back side of a second die.

Abstract: A method is provided, including following operations: identifying a first contact via, a second contact via, or a combination thereof in a first standard cell, wherein the first contact via is coupled between a first active region and a first conductive line on a first side, and the second contact via is coupled between a second active region and a second conductive line on a second side; calculating a first cell height according to a first width of the first and second active regions, and calculating a second cell height according to a second width of the first and second active regions; calculating multiple first available cell heights based on a ratio between the first and second cell heights; generating layout designs of multiple first cells; and manufacturing at least first one element in the integrated circuit based on the layout designs of the first cells.

Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.

Abstract: An integrated circuit includes a set of gates, a first, second and third conductive structure, and a first, second and third via. The set of gates includes a first, second and third gate. The first, second and third conductive structure extend in the first direction and are located on a second level. The first via couples the first conductive structure and the first gate. The second via couples the second conductive structure and the second gate. The third via couples the third conductive structure and the third gate. The first, second and third via are in a right angle configuration. The first and second gate are separated from each other by a first pitch. The first and third gate are separated from each other by a removed gate portion. The first and second conductive structure are separated from each other in the first direction.

Abstract: A method generating the layout diagram includes: selecting gate patterns for which a first distance from a corresponding VG pattern to a corresponding cut-gate section is equal to or greater than a first reference value; and for each of the selected gate patterns, increasing a size of the corresponding cut-gate section from a first value to a second value; the second value resulting in a first type of overhang of a corresponding remnant portion of the corresponding gate pattern; and the first type of overhang being a minimal permissible amount of overhang of the corresponding remnant portion beyond the corresponding first or second nearest active area pattern. A result is that gaps between corresponding ends of remnant portion of gate patterns are expanded.

Abstract: A method is provided, including following operations: obtaining information on gate pitch and a ratio between the gate pitch and a first metal line pitch; comparing a preset metal line end spacing with a second metal line pitch, of multiple metal traces, and a spacing between a metal line layer and a power rail layer; in response to the comparison, defining multiple first metal line patterns overlapping multiple first gate patterns and defining multiple second metal line patterns disposed between two adjacent gate patterns in multiple second gate patterns; placing the first metal line patterns in a first row in a floorplan of an integrated circuit layout design and the second metal line patterns in a second row, adjacent the first row; and manufacturing at least one element in an integrated circuit based on the integrated circuit layout design.

Abstract: A method of making an integrated includes steps of etching an opening in an insulating mask to expose a first dummy contact on a backside of the integrated circuit, depositing a conductive material into the opening, the conductive material contacting a sidewall of the first dummy contact, and recessing the conductive material to expose an end of the first dummy contact. The method also includes steps of depositing an insulating material over the conductive material in the opening, removing the first dummy contact from the insulating mask to form a first contact opening, and forming a first conductive contact in the first contact opening, the first conductive contact being electrically connected to the conductive material.