Abstract: Disclosed is a foldable touch screen electrode structure, including: a glass substrate including a first sidewall and a second sidewall opposite to each other in a thickness direction of the glass substrate, each of the first sidewall and the second sidewall being provided with an oxide layer; at least two upper adhesive layers and at least two lower adhesive layers; an upper metal grid layer adhered to the first sidewall through the at least two upper adhesive layers; a lower metal grid layer adhered to the second sidewall through the at least two lower adhesive layers; and an upper surface layer connected to an upper metal grid layer, and a lower surface layer connected to a lower metal grid layer; each of the upper surface layer and the lower surface layer includes a rough layer and a low reflection layer which are sequentially stacked.

Abstract: The disclosure discloses an intelligent terminal energy saving method based on artificial intelligence (AI) prediction. The method includes: collecting application (APP)-related operation data on the intelligent terminal; carrying out AI analysis on the APP-related operation data collected, to predict timing and a restriction measurement to restrict an APP in a background; and adopting the restriction measurement to restrict the APP in the background at the timing predicted. Corresponding to the method, the disclosure further discloses an intelligent terminal energy saving device based on AI prediction. Using the technical schemes disclosed in the disclosure, the power consumption of applications on a portable intelligent terminal can be reduced, and the battery life can be extended, without affecting the user experience.

Abstract: A high electron mobility transistor including a substrate; a channel layer on the substrate; an electron supply layer on the channel layer; a dielectric passivation layer on the electron supply layer; a gate recess in the dielectric passivation layer and the electron supply layer; a surface modification layer on an interior surface of the gate recess; and a P-type GaN layer in the gate recess and on the surface modification layer. The surface modification layer has a gradient silicon concentration.

Abstract: This application discloses a service data processing method and apparatus, to resolve a problem of low bandwidth utilization in the conventional technology. A dynamic framing method is used. When a transmission rate of an OTN data frame increases, a length of a payload area constantly increases, while a length of an overhead area does not increase. In other words, in OTN data frames at different transmission rates, lengths of overhead areas are fixed. As the transmission rates of the OTN data frames increase, lengths of payload areas constantly increase. In this way, when the rate increases, overheads do not occupy more bandwidths, thereby improving bandwidth utilization.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.

Abstract: A mobile device includes a ground element, a first radiation element, a second radiation element, and a dielectric substrate. The first radiation element has a feeding point. The first radiation element includes a meandering portion. The second radiation element is coupled to the feeding point, and is at least partially surrounded by the first radiation element. A coupling gap is formed between the first radiation element and the second radiation element. The ground element, the first radiation element, and the second radiation element are all disposed on the dielectric substrate. A planar antenna structure is formed by the first radiation element and the second radiation element. The planar antenna structure covers a TETRA (Terrestrial Trunked Radio) frequency band and a GPS (Global Positioning System) frequency band.

Abstract: A foldable tool includes a first rod member, a second rod member and a pivoting device. The first rod member has a first length. The second rod member has a second length. The pivoting device is arranged between the first rod member and the second rod member. The first rod member and the second rod member are configured to be selectively pivotable to each other via the first pivoting device. A ratio of the first length to the second length is in a range between 1.1 and 6.

Abstract: Temperature data acquired from a wearable device, for example at a user's wrist or within the device itself, can be used as a proxy to evaluate core body temperature changes. Sensor data may be provided to determine a skin temperature of a user and also an internal device temperature. A correlation between these two temperatures may be used to monitor subsequent temperature changes, which may be indicative of changes in the user's core body temperature. Temperature changes to the proxy temperature may be evaluated against a threshold to determine whether the user's core body temperature has also increased, which may be indicative of one or more physiological symptoms or events. Furthermore, additional physiological variables such as respiration rate, nocturnal heart rate, and heart rate variability may be analyzed for early signs of impending illness. A trained machine learning classifier can output the predicted illness status of an individual based on these parameters.

Abstract: A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.

Abstract: Methods and apparatuses for mapping processing and de-mapping processing in an optical transport network are provided. A Low Order Optical Channel Data Unit (LO ODU) signal is mapped into a payload area of an Optical Channel Data Tributary (ODTU) signal in units of M bytes. M is equal to the number of time slots of a High Order Optical Channel Payload Unit (HO OPU) that are to be occupied by the ODTU signal, and M is an integer larger than 1. Overhead information is encapsulated to an overhead area of the ODTU signal. Thereafter, the ODTU signal is multiplexed into the HO OPU. According to the application, an efficient and universal mode for mapping the LO ODU to the HO OPU is provided.

Abstract: Embodiments of the present disclosure provide a data transmission method, which meets a requirement for an Ethernet network with diversified rate levels. The method includes: grouping media access control (MAC) layer data into a plurality of MAC layer data groups; allocating, according to a bandwidth required by a target MAC layer data group and a reference bandwidth of a logical channel, at least one target logical channel to the target MAC layer data group; encoding the target MAC layer data group to generate target physical layer data, where the target logical channel corresponds to the target MAC layer data group and the target physical layer data; and sending the target physical layer data and first indication information, where the first indication information is used to indicate a relationship between the target physical layer data and the target logical channel.

Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is first subjected to the nitride treatment and is then subjected to the oxidation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.

Abstract: A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.

Abstract: A multimode clutch assembly is positioned in a powertrain of a rotorcraft. The clutch assembly includes a freewheeling unit having a driving mode in which torque applied to the input race is transferred to the output race and an overrunning mode in which torque applied to the output race is not transferred to the input race. A bypass assembly has an engaged position that couples the input and output races of the freewheeling unit. An actuator assembly shifts the bypass assembly between engaged and disengaged positions. An engagement status sensor is configured to determine the engagement status of the bypass assembly. In the disengaged position, the overrunning mode of the freewheeling unit is enabled such that the clutch assembly is configured for unidirectional torque transfer. In the engaged position, the overrunning mode of the freewheeling unit is disabled such that the clutch assembly is configured for bidirectional torque transfer.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.