Patents by Inventor Wei Su

Wei Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230140279
    Abstract: An inter-processor communication method, an electronic assembly, and an electronic device are provided. The electronic device at least includes a first core and a second core. A plurality of communication channels is defined between the first core and the second core. Each of the plurality of communication channels having a communication performance different from each other. The inter-processor communication method includes: acquiring to-be-transmitted data, the to-be-transmitted data is data transmitted between the first core and the second core; acquiring a corresponding communication channel corresponding to the to-be-transmitted data from the plurality of communication channels as a target communication channel; transmitting the to-be-transmitted data via the target communication channel.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 4, 2023
    Inventors: Dingyi LI, Libin ZHOU, Liang WANG, Jinze GAO, Jianhui HUANG, Qiming LI, Wei SU
  • Publication number: 20230135072
    Abstract: The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 4, 2023
    Applicant: United Microelectronics Corp.
    Inventors: Hao Che Feng, Hung Jen Huang, Hsin Min Han, Shih-Wei Su, Ming Shu Chiu, Pi-Hung Chuang, Wei-Hao Huang, Shao-Wei Wang, Ping Wei Huang
  • Publication number: 20230122525
    Abstract: Embodiments of the present invention disclose a data frame transmission method and a related device. The method includes: first, generating a data frame, where an overhead area of the data frame includes a target bit, the target bit simultaneously indicates at least two multiframes, the multiframe includes a plurality of consecutive data frames, different multiframes include different quantities of data frames, different overhead information is inserted into the different multiframes, and the data frame is an optical transport network OTN data frame; and then sending the data frame.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 20, 2023
    Inventors: Wei Su, Liang Sun, Qiuyou Wu
  • Publication number: 20230120045
    Abstract: Disclosed is a foldable touch screen electrode structure, including: a glass substrate including a first sidewall and a second sidewall opposite to each other in a thickness direction of the glass substrate, each of the first sidewall and the second sidewall being provided with an oxide layer; at least two upper adhesive layers and at least two lower adhesive layers; an upper metal grid layer adhered to the first sidewall through the at least two upper adhesive layers; a lower metal grid layer adhered to the second sidewall through the at least two lower adhesive layers; and an upper surface layer connected to an upper metal grid layer, and a lower surface layer connected to a lower metal grid layer; each of the upper surface layer and the lower surface layer includes a rough layer and a low reflection layer which are sequentially stacked.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 20, 2023
    Applicant: Micron Optoelectronics Co., Ltd.
    Inventors: Wei SU, Zonghe YE
  • Publication number: 20230121087
    Abstract: A socket adaptor includes a shank, a body movably mounted on the shank, a detent movably arranged between the shank and the body, and a magnetic device. The magnetic device includes a limiting member and a magnetic member. The limiting member has a proximal end fixed to an end of the shank, a distal end opposite to the proximal end, and a containing hole formed at the distal end. The magnetic member is arranged in the containing hole.
    Type: Application
    Filed: August 1, 2022
    Publication date: April 20, 2023
    Inventor: Cheng-Wei SU
  • Publication number: 20230105013
    Abstract: An isolated or engineered polypeptide, a microorganism comprising a nucleic acid sequence encoded by the polypeptide, and a method for synthesizing a polyphenolic phytochemicals phosphate derivative using the polypeptide or the microorganism are provided. The polypeptide having a homologous protein sequence that is more than 70% identical to the polyphenol phosphorylation synthetase (SEQ ID NO: 13) comprises a conserved domain which sequentially comprises: an ATP-binding domain, which includes active catalytic sites of Lys27, Arg102, and Glu282; a substrate-binding domain, which includes a conserved motif of DDHHFYIDAMLDAKAR (SEQ ID NO: 14), and includes active catalytic sites ofAsp627, His629, and His630; and a phosphorylated histidine catalytic domain, which includes His795 based on SEQ ID NO: 13.
    Type: Application
    Filed: June 29, 2022
    Publication date: April 6, 2023
    Inventors: NAN-WEI SU, CHEN HSU
  • Patent number: 11612438
    Abstract: A navigation method for a medical operation and implemented by a robotic system is provided. The method includes the steps of: receiving, at a processor of the robotic system, at least one set of navigation data; receiving or generating at least one three-dimensional model of the virtual object in the navigation data; calculating the navigation data to generate a virtual environment and at least one navigation instruction; and presenting, at a user interface associated with the robotic system, the virtual environment and/or the navigation instruction to a user of the robotic system for the user to refer to during the medical operation.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 28, 2023
    Assignee: POINT ROBOTICS MEDTECH INC.
    Inventors: Shou-An Yu, Bang-Hao Dai, Che-Wei Su, Hao-Kai Chou, Chia-Ho Yen, Chih-Min Yang, Shyue-Cherng Juang
  • Patent number: 11612737
    Abstract: A non-contact muscle signal sensing and assisting device, comprises a radar sensing module, a microprocessor and an electrical stimulation module. The radar sensing module continuously transmits a first microwave signal to a muscle bundle part and receives a corresponding reflected muscle signal, and performs a demodulation procedure on a second microwave signal and the reflected muscle signal to obtain and output a demodulated muscle signal. The microprocessor performs a muscle-movement signal characteristic processing procedure on the demodulated muscle signal to obtain a characterized muscle signal. The microprocessor obtains a muscle movement parameter according to the characterized muscle signal and controls the electrical stimulation module to emit a micro electrical stimulation signal to stimulate a reflex nerve when the muscle movement parameter fits an assistive condition, thereby stimulate muscle movement.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: March 28, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hong-Dun Lin, Tai-Wei Su, Chun-Kai Chang
  • Patent number: 11607783
    Abstract: Circlip pliers comprise a first plier and a second plier. The first plier is provided with an external connection portion, an internal connection portion, and a pivot portion located between the external connection portion and the internal connection portion. The second plier is provided with an external connection portion, an internal connection portion, and a second pivot portion located between the second external connection portion and the second internal connection portion. The external connection portions are adapted to insert into grip holes in an external circlip. The internal connection portions are adapted to insert into grip holes in an internal circlip. The first and second pivot portions are pivotally connected with each other.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: March 21, 2023
    Assignee: Hong Ann Tool Industries Co., Ltd.
    Inventor: Cheng-Wei Su
  • Publication number: 20230073772
    Abstract: A wrench extender includes an extension member and a retaining member. The extension member has a wrench supporting base with a supporting face and first and second sides adjacent to the supporting face and respectively disposed at two opposite sides of the supporting face. The wrench supporting base is provided with a first holding portion arranged on the supporting face and adjacent to the first side, and a second holding portion arranged on the supporting face and adjacent to the second side. The retaining member is arranged on the wrench supporting base to retain a wrench hold by the wrench supporting base.
    Type: Application
    Filed: August 24, 2022
    Publication date: March 9, 2023
    Inventor: Cheng-Wei SU
  • Patent number: 11599600
    Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.
    Type: Grant
    Filed: September 6, 2020
    Date of Patent: March 7, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
  • Publication number: 20230064914
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Yu-Chu LIN, Wen-Chih CHIANG, Chi-Chung JEN, Ming-Hong SU, Mei-Chen SU, Chia-Wei LEE, Kuan-Wei SU, Chia-Ming PAN
  • Publication number: 20230065897
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Yu-Chu LIN, Wen-Chih CHIANG, Chi-Chung JEN, Ming-Hong SU, Mei-Chen SU, C.W. LEE, Kuan-Wei SU, Chia-Ming PAN
  • Publication number: 20230063119
    Abstract: A method for deduplication applicable to a file chunked into a plurality of deduplicated chunks is provided and includes: defining a calculation range in the file according to types of the chunks in the file, where the calculation range includes a plurality of consecutive chunks in the file; generating an evaluation value according to the types of the chunks in the calculation range to determine whether to mark the chunks in the calculation range; and re-chunking and deduplicating the marked chunks in the file. A computer-readable medium and a file system corresponding to the method for deduplication are also provided.
    Type: Application
    Filed: November 9, 2021
    Publication date: March 2, 2023
    Inventors: Tsung-Han Chiang, Jing-Wei Su, Chin-Tsung Cheng
  • Publication number: 20230067563
    Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy structures spaced apart from each other, forming a plurality of dielectric spacers laterally covering the dummy structures to form a plurality of trenches defined by the dielectric spacers, filling an conductive material into the trenches to form electrically conductive features, selectively depositing a capping material on the electrically conductive features to form a capping layer, removing the dummy structures to form a plurality of recesses defined by the dielectric spacers, filling a sacrificial material into the recesses so as to form sacrificial features, depositing a sustaining layer on the sacrificial features, and removing the sacrificial features to form air gaps confined by the sustaining layer and the dielectric spacers.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei SU, Chia-Tien WU, Hsin-Ping CHEN, Shau-Lin SHUE
  • Publication number: 20230067527
    Abstract: A semiconductor structure includes a substrate, a dielectric layer, a first conductive feature and a second conductive feature. The substrate includes a semiconductor device. The dielectric layer is disposed on the substrate. The first conductive feature is formed in the first dielectric layer. The second conductive feature penetrates the first conductive feature and the dielectric layer, and is electrically connected to the first conductive feature and the semiconductor device.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Chen CHU, Chia-Tien WU, Chia-Wei SU, Yu-Chieh LIAO, Chia-Chen LEE, Hsin-Ping CHEN, Shau-Lin SHUE
  • Patent number: 11594645
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chu Lin, Wen-Chih Chiang, Chi-Chung Jen, Ming-Hong Su, Mei-Chen Su, Chia-Wei Lee, Kuan-Wei Su, Chia-Ming Pan
  • Patent number: 11595130
    Abstract: Embodiments of the present invention provide a method and an apparatus for transmitting and receiving a client signal in an optical transport network. In the transmission method, a received client signal is mapped into a variable-rate container OTU-N, wherein a rate of the OTU-N is N times as high as a preset reference rate; and then, the variable-rate container OTU-N is split into N optical stab-channel transport units OTUsubs by column, where a rate of each OTUsub equals to the reference rate; next, the N optical sub-channel transport units OTUsubs are modulated onto one or more optical carriers; at last, the one or more optical carriers is transmitted through a fiber.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: February 28, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Wei Su, Qiuyou Wu, Limin Dong
  • Publication number: 20230054559
    Abstract: An utility knife includes a housing, a blade seat, a blade, and a switching assembly. The housing has a chamber, an opening formed at an end of the chamber, and a switch slot communicating with the chamber. The blade seat is arranged in the chamber and has a blade holding slot and a guiding slot communicating with the blade holding slot. The blade is detachably mounted to the blade holding slot and has at least one engaging slot. The switching assembly includes a toggle switch movably arranged to the switch slot and exposed to the housing, an engaging block disposed at an end of the toggle switch and movably arranged to the guiding slot, and a biasing member elastically biasing the engaging block relative to the guiding slot.
    Type: Application
    Filed: March 17, 2022
    Publication date: February 23, 2023
    Inventor: Cheng-Wei SU
  • Patent number: D979530
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: February 28, 2023
    Assignee: Logitech Europe S.A.
    Inventors: Chun-Wei Su, Yuzheng Lu, Shelly Chen, Richard Hu, Ku Chieh