Abstract: A medical image analysis system comprises: a database for storing a first medical image data indicating a target medical image; and a server for accessing the database. The server includes: a first analysis module for generating a first determination data according to the first medical image data; a second analysis module for generating a second determination data according to the first medical image data; and an ensemble module communicatively connected with the first and second analysis modules and generating a third determination data according to the first and second determination data. The first and second determination data each indicate whether the target medical image includes a cancerous tissue image or indicate a chance of the target medical image including a cancerous tissue image. The third determination data indicates whether the target medical image includes a cancerous tissue image.

Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.

Abstract: A device structure includes a first electrode overlying a substrate; a node dielectric contacting the first electrode and including a dielectric material having a dielectric constant greater than 30; and a second electrode contacting the node dielectric. A first one of the first electrode and the second electrode includes a first catalytic metal plate in direct contact with the node dielectric and having a first electronegativity that is not greater than an electronegativity of molybdenum.

Abstract: A time division duplexed (TDD) frequency modulation continuous wave (FMCW) radar system includes P transmitter circuit chains and M receiver circuit chains. The P transmitter circuit chains are used to transmit a plurality of FMCW signals. A pth transmitter circuit chain is coupled to a single pole Op throw (SPQPT) radio frequency (RF) switch, the SPOT RF switch is coupled to Op antennas, Qp and P are positive integers, and p is a positive integer not larger than P. The M receiver circuit chains are used to receive a plurality of reflected FMCW signals. An mth receiver circuit chain is coupled to a single pole Nm throw (SPNmT) radio frequency (RF) switch, the SPNmT RF switch is coupled to Nm antennas, Nm and M are positive integers, and m is a positive integer not larger than M.

Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

Abstract: A side-wettable package with edge-recessed bond pads has a composite substrate, and the composite substrate is covered with a molding layer. An upper redistribution layer is formed on the molding layer, and the upper redistribution layer is covered with a solder mask and part of the upper redistribution is exposed to form at least one surface bond pad. Surfaces of each surface bond pad are formed with an anti-oxidation conductive layer, wherein at least one side surface of each surface bond pad is recessed relative to side surfaces of the molding layer. The present invention does not form the side-wettable structure by cutting the upper redistribution layer to prolong service life of cutting Wheels and structural stability of the package. The anti-oxidation conductive layer increases a contacting area between solder and each surface bond pad, thereby facilitating AOI instruments to determine soldering condition of the package and another component.

Abstract: An electronic device is provided. The electronic device includes a panel, a protective substrate, and a first light-shielding structure. The panel has an active area and a peripheral area. The peripheral area is adjacent to the active area. The protective substrate is disposed opposite to the panel. The first light-shielding structure is disposed on a surface of the protective substrate and corresponds to the peripheral area. A portion of the first light-shielding structure that overlaps the peripheral area has at least one opening.

Abstract: A memory structure and methods for operating memory structures are provided. The memory structure includes a first, a second and a third gate structures disposed along a first direction and separated from each other, channel bodies having first ends and second ends, source regions separated from each other, having first conductivity types and connected to the first ends of the channel bodies respectively, drain regions separated from each other, having second conductivity types and connected to the second ends of the channel bodies respectively, and first side plugs disposed along a second direction, extending along a third direction, and electrically connected to the source regions and the channel bodies. The first gate structure includes island structures disposed along the second direction and extending along the third direction.

Abstract: A semiconductor package includes a semiconductor element, at least one electronic die, at least one optical die, an encapsulant, and a substrate. The semiconductor element has a first side and a second side opposing to the first side. The at least one electronic die is disposed over the first side. The at least one optical die is disposed over the first side and next to the at least one electronic die. The encapsulant is disposed on the first side and covers the at least one electronic die, where a sidewall of the at least one optical die is distant from the encapsulant, and a sidewall of the encapsulant is aligned with a sidewall of the semiconductor element. The substrate is disposed over the second side, where the at least one electronic die is electrically coupled to the substrate and the at least one optical die through the semiconductor element.

Abstract: A package capable of eliminating bubble formation includes a composite substrate having an accommodating space, an upper conductive layer and a lower conductive layer; at least one conductive via formed in the composite substrate and electrically connected to the upper conductive layer and the lower conductive layer; a die mounted in the accommodating space and having a first surface and a second surface; a molding layer covering the composite substrate and filled in the at least one conductive via and the accommodating space to wrap the die; the support layer buried in the molding layer and located above the upper conductive layer; a redistribution layer mounted on the molding layer and electrically connected to the first surface of the die and the upper conductive layer; wherein the molding layer is formed by laminating a first insulating sheet and a second insulating sheet.

Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

Abstract: An antenna device includes a differential-line, a first metal and a second metal. The differential-line includes a first line and a second line. The first metal and second metal are coupled to the first line and second line respectively. The first metal and second metal have different shapes and/or different sizes. The first metal and second metal form symmetric or asymmetric dipole. The first metal and second metal can be disposed on the same plane or different planes, can be electrically insulated and can have a first slot and a second slot respectively. The antenna device can further include a base coupled to the first line and second line. The base can be a daughter board having a front-end module or not. The IC package in daughter board can have different sizes. The daughter board can be offset by different distances and can be coupled to a mother board.

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: A semiconductor device and methods of forming the semiconductor device are described herein and are directed towards forming a source/drain contact plug for adjacent finFETs. The source/drain regions of the adjacent finFETs are embedded in an interlayer dielectric and are separated by an isolation region of a cut-metal gate (CMG) structure isolating gate electrodes of the adjacent finFETs The methods include recessing the isolation region, forming a contact plug opening through the interlayer dielectric to expose portions of a contact etch stop layer disposed over the source/drain regions through the contact plug opening, the contact etch stop layer being a different material from the material of the isolation region. Once exposed, the portions of the CESL are removed and a conductive material is formed in the contact plug opening and in contact with the source/drain regions of the adjacent finFETs and in contact with the isolation region.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A semiconductor device includes a substrate, a plurality of memory arrays and a plurality of capacitors. The substrate includes a plurality of memory array regions. Each memory array region includes a plurality of memory blocks and a plurality of dummy blocks. The dummy blocks are located along a boundary of the memory blocks. The plurality of memory arrays are disposed in the plurality of memory blocks. The plurality of capacitors are disposed in the plurality of dummy blocks along the boundary of the plurality of memory blocks. The plurality of memory arrays may include 3D NAND flash memories with high capacity and high performance.

Abstract: In a radar sensor, a transmitting antenna is configured to radiate a transmitted RF signal, a receiving antenna is configured to receive a reflected RF signal from a target, and a frontend circuit is configured to calculate the distance between the target and the radar sensor by measuring the frequency shift between the transmitted RF signal and the reflected RF signal. The frontend circuit includes a crystal-less signal synthesizer configured to generate the transmitted RF signal without using a crystal, and a mixer configured to provide an IF-band signal associated with the frequency shift between the transmitted RF signal and the reflected RF signal by mixing the reflected RF signal and the transmitted RF signal.

Abstract: A projection lens includes a first and a second optical lens assembly. The first optical lens assembly is configured to transmit an image beam to the second optical lens assembly, which projects out the image beam from the projection lens. The second optical lens assembly includes a first and a second reflective element, and an optical member disposed between the first and the second reflective element and including a translucent region and a reflective region. The first reflective element is configured to reflect the image beam from the first optical lens assembly and transmit to the translucent region, which allows the image beam from the first reflective element to pass through and transmit to the second reflective element. The second reflective element is configured to reflect the image beam from the translucent region and transmit to the reflective region, which reflects the image beam from the second reflective element.

Abstract: Methods for making a semiconductor device using an improved BARC (bottom anti-reflective coating) are provided herein. The improved BARC comprises a polymer formed from at least a styrene monomer having at least one or two hydrophilic substituents. The monomer(s) and substituents can be varied as desired to obtain a balance between film adhesion and wet etch resistance. Also provided is a semiconductor device produced using such methods.