Abstract: A package capable of eliminating bubble formation includes a composite substrate having an accommodating space, an upper conductive layer and a lower conductive layer; at least one conductive via formed in the composite substrate and electrically connected to the upper conductive layer and the lower conductive layer; a die mounted in the accommodating space and having a first surface and a second surface; a molding layer covering the composite substrate and filled in the at least one conductive via and the accommodating space to wrap the die; the support layer buried in the molding layer and located above the upper conductive layer; a redistribution layer mounted on the molding layer and electrically connected to the first surface of the die and the upper conductive layer; wherein the molding layer is formed by laminating a first insulating sheet and a second insulating sheet.

Abstract: A semiconductor package includes a semiconductor element, at least one electronic die, at least one optical die, an encapsulant, and a substrate. The semiconductor element has a first side and a second side opposing to the first side. The at least one electronic die is disposed over the first side. The at least one optical die is disposed over the first side and next to the at least one electronic die. The encapsulant is disposed on the first side and covers the at least one electronic die, where a sidewall of the at least one optical die is distant from the encapsulant, and a sidewall of the encapsulant is aligned with a sidewall of the semiconductor element. The substrate is disposed over the second side, where the at least one electronic die is electrically coupled to the substrate and the at least one optical die through the semiconductor element.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: An antenna device includes a differential-line, a first metal and a second metal. The differential-line includes a first line and a second line. The first metal and second metal are coupled to the first line and second line respectively. The first metal and second metal have different shapes and/or different sizes. The first metal and second metal form symmetric or asymmetric dipole. The first metal and second metal can be disposed on the same plane or different planes, can be electrically insulated and can have a first slot and a second slot respectively. The antenna device can further include a base coupled to the first line and second line. The base can be a daughter board having a front-end module or not. The IC package in daughter board can have different sizes. The daughter board can be offset by different distances and can be coupled to a mother board.

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

Abstract: A semiconductor device and methods of forming the semiconductor device are described herein and are directed towards forming a source/drain contact plug for adjacent finFETs. The source/drain regions of the adjacent finFETs are embedded in an interlayer dielectric and are separated by an isolation region of a cut-metal gate (CMG) structure isolating gate electrodes of the adjacent finFETs The methods include recessing the isolation region, forming a contact plug opening through the interlayer dielectric to expose portions of a contact etch stop layer disposed over the source/drain regions through the contact plug opening, the contact etch stop layer being a different material from the material of the isolation region. Once exposed, the portions of the CESL are removed and a conductive material is formed in the contact plug opening and in contact with the source/drain regions of the adjacent finFETs and in contact with the isolation region.

Abstract: In a radar sensor, a transmitting antenna is configured to radiate a transmitted RF signal, a receiving antenna is configured to receive a reflected RF signal from a target, and a frontend circuit is configured to calculate the distance between the target and the radar sensor by measuring the frequency shift between the transmitted RF signal and the reflected RF signal. The frontend circuit includes a crystal-less signal synthesizer configured to generate the transmitted RF signal without using a crystal, and a mixer configured to provide an IF-band signal associated with the frequency shift between the transmitted RF signal and the reflected RF signal by mixing the reflected RF signal and the transmitted RF signal.

Abstract: A semiconductor device includes a substrate, a plurality of memory arrays and a plurality of capacitors. The substrate includes a plurality of memory array regions. Each memory array region includes a plurality of memory blocks and a plurality of dummy blocks. The dummy blocks are located along a boundary of the memory blocks. The plurality of memory arrays are disposed in the plurality of memory blocks. The plurality of capacitors are disposed in the plurality of dummy blocks along the boundary of the plurality of memory blocks. The plurality of memory arrays may include 3D NAND flash memories with high capacity and high performance.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: Methods for making a semiconductor device using an improved BARC (bottom anti-reflective coating) are provided herein. The improved BARC comprises a polymer formed from at least a styrene monomer having at least one or two hydrophilic substituents. The monomer(s) and substituents can be varied as desired to obtain a balance between film adhesion and wet etch resistance. Also provided is a semiconductor device produced using such methods.

Abstract: A projection lens includes a first and a second optical lens assembly. The first optical lens assembly is configured to transmit an image beam to the second optical lens assembly, which projects out the image beam from the projection lens. The second optical lens assembly includes a first and a second reflective element, and an optical member disposed between the first and the second reflective element and including a translucent region and a reflective region. The first reflective element is configured to reflect the image beam from the first optical lens assembly and transmit to the translucent region, which allows the image beam from the first reflective element to pass through and transmit to the second reflective element. The second reflective element is configured to reflect the image beam from the translucent region and transmit to the reflective region, which reflects the image beam from the second reflective element.

Abstract: EUV masks and methods of fabrication thereof are described herein. An exemplary method includes receiving an EUV mask having a multilayer structure, a capping layer disposed over the multilayer structure, a patterned absorber layer disposed over the capping layer, and a patterned hard mask disposed over the patterned absorber layer. The method further includes removing the patterned hard mask by performing a first etching process to partially remove the patterned hard mask and performing a second etching process to remove a remainder of the patterned hard mask. The first etching process uses a first etchant, and the second etching process uses a second etchant. The second etchant is different than the first etchant. In some embodiments, the first etchant is a halogen-based plasma (e.g., a Cl2 plasma), and the second etchant is a halogen-and-oxygen-based plasma (e.g., a Cl2+O2 plasma).

Abstract: A method of forming a semiconductor device includes: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the via; selectively forming a capping layer over the upper surface of the via, where the capping layer has a curved upper surface that extends above a first upper surface of the first dielectric layer distal from the substrate; after forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming an electrically conductive material over the barrier layer.

Abstract: A semiconductor package includes an interposer that has a first side and a second side opposing the first side. A semiconductor device that is on the first side of the interposer and an optical device that is on the first side of the interposer and next to the semiconductor device. A first encapsulant layer includes a first portion and a second portion. The first portion of the first encapsulant layer is on the first side of the interposer and along sidewalls of the semiconductor device. A gap is between a first sidewall of the optical device and a second sidewall of the first portion of the first encapsulant layer. A substrate is over the second side of the interposer. The semiconductor device and the optical device are electrically coupled to the substrate through the interposer.

Abstract: An axial-flow heat-dissipation fan including a frame and a blade wheel is provided. The frame has an inlet, an outlet, and an inner wall connected between the inlet and the outlet. The inner wall surrounding the blade wheel has at least one rough region. The blade wheel is rotatably disposed in the frame and located between the inlet and the outlet, and an air flows into the frame via the inlet and flows out of the frame via the outlet by rotation of the blade wheel. A gap exists between a blade end of the blade wheel and the inner wall. A laminar flow is generated at the gap when the blade wheel is rotating and the blade end passes through the rough region so as to prevent a backflow generated at the gap, wherein a flowing direction of the backflow is opposite to a flowing direction of the air flow.

Abstract: A projection device includes a light source module, a display panel, a freeform-surface reflective mirror, and a projection lens. The light source module includes a light source, a first Fresnel lens element, and a second Fresnel lens element. The first Fresnel lens element and the second Fresnel lens element are parallel to each other and located between the light source and the display panel. The display panel is arranged between the light source module and the freeform-surface reflective mirror. The projection lens is configured to transmit an image beam out of the projection device, and a direction of an optical axis of the projection lens is different from a direction of a normal of the first Fresnel lens element.

Abstract: A method and system for establishing a model for sensing ions in a solution, and a method and system for sensing ions in a solution apply an ion-sensitive field effect transistor in a machine learning model for ion detection in training solutions. The method for establishing a model includes adjusting environmental parameters, where the environmental parameters are selected from any one of multiple target temperatures or from any one of multiple external electric fields; establishing at least one virtual sensor based on the biasing relationship of the multi-gate ion sensitive field effect transistor; obtaining, by the at least one virtual sensor, multiple training features of the training solution based on the environmental parameters and bias parameters; and loading, by a computer, the environmental parameters and the training features into a machine learning model to establish an ion detection model, which is used to sense the types and concentrations of ions.

Abstract: Methods, devices, systems, and apparatus for three-dimensional semiconductor structures are provided. In one aspect, a semiconductor device includes: a semiconductor substrate, multiple conductive layers vertically stacked on the semiconductor substrate, and multiple transistors. The multiple conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked together. The multiple transistors include a first transistor and a second transistor in the first conductive layer and a third transistor in the third conductive layer. Each transistor includes a first terminal, a second terminal, and a gate terminal. First terminals of the first, second, and third transistors are conductively coupled to a first conductive node in the second conductive layer.

Abstract: Polarization-insensitive metasurfaces using anisotropic nanostructures are disclosed. These anisotropic structures allow for an accurate implementation of phase, group delay, and group delay dispersion, while simultaneously making it possible to realize a polarizationinsensitive, diffraction-limited and achromatic metalens for wavelength, e.g., ?=from about 460 nm to about 700 nm. The approach of polarization-insensitivity can be also applied for other metasurface devices with applications in, e.g., imaging and virtual or augmented reality.