Patents by Inventor Wei-Ting Lin

Wei-Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10448013
    Abstract: Encoding or decoding blocks of video frames using multiple reference frames with adaptive temporal filtering can include generating one or more candidate reference frames by applying temporal filtering to one or more frames of a video sequence according to relationships between respective ones of the one or more frames and a current frame of the video sequence. A reference frame to use for predicting the current frame can be selected from the one or more candidate reference frames, and a prediction block can be generated using the selected reference frame. During an encoding operation, the prediction block can be used to encode a block of a current frame of the video sequence. During a decoding operation, the prediction block can be used to decode a block of a current frame of the video sequence.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 15, 2019
    Assignee: GOOGLE LLC
    Inventors: Debargha Mukherjee, Yaowu Xu, James Bankoski, Paul Wilkins, Jingning Han, Yuxin Liu, Wei-Ting Lin
  • Patent number: 10424622
    Abstract: A display device comprised of OLEDs and micro LEDs which allows for blue light degradation of the OLEDs includes a first substrate and a second substrate in a double-decked configuration. First light emitting elements are located and spaced on the first substrate and second light emitting elements are located and spaced on the second substrate, the light emitting elements on the lower deck being staggered so as not to be hidden by the light emitting elements on the upper deck. The upper deck has openings (or is transparent) therein to allow egress of light from the light emitting elements of the lower deck. The display device provides a solution for uneven display cause by degradation of pixels.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: September 24, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chang-Ting Lin, Wei-Chih Chang, Ying-Chieh Chen, Chung-Wen Lai, Chun-Chieh Huang, Wei-Li Wang, Po-Yi Lu, Jen-Jie Chen, I-Wei Wu
  • Patent number: 10424844
    Abstract: An electronic device includes a housing. The housing defines a slot and a groove communicating with the slot. The housing is divided into at least a first radiating portion and a second radiating portion by the slot and the groove. The first radiating portion is spaced apart from the second radiating portion. The first radiating portion and the second radiating portion cooperatively serve as an antenna structure of the electronic device to receive and/or transmit wireless signals. The electronic device further performs a predetermined function through the groove.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: September 24, 2019
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Kwang-Pi Lee, Wei-Ting Cheng, Yen-Hui Lin, Szu-Tso Lin
  • Publication number: 20190250673
    Abstract: An electronic device includes a first body, a second body, a base, a first shaft structure, a second shaft structure, and a locking component. The second body is connected to the first body through the base. The first shaft structure includes a first shaft and a second shaft. The second body is pivoted to a first base portion of the base through the first shaft and a second base portion of the base through the second shaft. The second shaft structure includes a connecting component fixed to the first body and a third shaft pivoted to the first base portion and the connecting component. The first and second shafts are perpendicular to the third shaft. The locking component is slidably disposed between the second base portion and the first body and configured to lock or release a connection between the second base portion and the first body.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 15, 2019
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Ting Chen, Tzu-Chien Lai, Yen-Hsiao Yeh, Nien-Chen Lee, Yi-Chun Lin
  • Patent number: 10365442
    Abstract: An optical housing for high power fiber components includes an upper cover, a lower base, and two isolating members. The upper cover includes a light-reflecting portion for containing the optical fiber and receiving and reflecting the light therefrom. The lower base is connected with the upper cover and includes a light-receiving portion which corresponds to the light-reflecting portion in position and surrounds the optical fiber, thereby receives the light from the light-reflecting portion. The isolating members are disposed between the upper cover and the lower base and located on two sides of the optical housing to prevent the leakage of light from the optical fiber.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 30, 2019
    Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Chiang-Hsin Lin, Wei-Ting Lin, Jian-Hung Lin, Po-Tse Tai, Wei-Chung Yen
  • Publication number: 20190206843
    Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.
    Type: Application
    Filed: March 8, 2019
    Publication date: July 4, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Li-Hao LYU, Chieh-Ju TSAI, Yu-Kai LIN, Wei-Ming HSIEH, Yu-Pin TSAI, Man-Wen TSENG, Yu-Ting LU
  • Publication number: 20190178809
    Abstract: A detecting method for a workpiece surface includes the following steps. Firstly, a workpiece is provided with a first environment, wherein the first environment has a first environmental temperature higher than a first saturation temperature corresponding to an environmental-relative humidity. Then, the workpiece is provided with a second environment, wherein the second environment has a second environmental temperature lower than the first environmental temperature, such that a itself-temperature of the workpiece reduces to a mist temperature, wherein the mist temperature is substantially equal to or higher than the second environmental temperature. Then, the workpiece is provided with a mist environment, wherein the mist environment has a mist-saturation temperature corresponding to a mist-environmental relative humidity is equal to or higher than the mist temperature for misting a surface of the workpiece. Then, the surface of the misted workpiece is detected.
    Type: Application
    Filed: February 14, 2019
    Publication date: June 13, 2019
    Inventors: Wei-Yao CHIU, Kuo-Feng HUNG, Yu-Ting LIN, Keng-Hao CHANG
  • Publication number: 20190181135
    Abstract: A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang HUANG, Shang-Chuan PAI, Wei-Chung WU, Szu-Chi CHEN, Sheng-Chih CHUANG, Yin-Ting LIN, Pei-Chun YU, Han-Pei LIU, Jung-Tsun CHUANG, Chieh-Yao CHUANG, Hung-Wei CHEN
  • Publication number: 20190179287
    Abstract: A spindle with intelligent auto-detection system may comprise a spindle, a shell configured for covering the spindle, a first conducting ring, a second conducting ring and at least a sensor. The spindle has a connecting section and a working section, and the connecting section is configured for connecting a power unit of a processing machine. Moreover, a tool is secured on the working section, and the sensor is positioned in an inner tube of the spindle. The first conducting ring and the second conducting ring in a recess of the shell are respectively electrically connected to the sensor and an analytical instrument. When the spindle is spinning, the sensor is adapted to measure various data of statuses of the spindle and the processing machine, and the obtained data is configured to be sent to the analytical instrument, thereby achieving monitoring effect.
    Type: Application
    Filed: December 8, 2017
    Publication date: June 13, 2019
    Inventor: Wei-Ting Lin
  • Publication number: 20190172345
    Abstract: The present disclosure provides a system and a method for detecting a dangerous vehicle. This method includes steps as follows. Vehicle detectors spaced apart from each other are provided, and each vehicle detector obtains a traffic image. The server infers the interaction among the vehicles in the traffic image according to a car-following theory, so as to find at least one outlier vehicle from the vehicles and to select the outlier vehicle as a focus vehicle to be tracked. The server determines whether the driving behavior of the focus vehicle falls into an abnormal behavior model.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 6, 2019
    Inventors: Chi-Sheng LIN, Chien LEE, Wei-Lun HSIAO, Yu-Ting HSU
  • Publication number: 20190164882
    Abstract: A semiconductor device includes a substrate, a dielectric region, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The plurality of conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and is electrically connected to a first conductive region of the plurality of conductive regions. The conductive structure is arranged to penetrate through the substrate and formed under the first conductive rail. The conductive structure is electrically connected to the first conductive rail.
    Type: Application
    Filed: May 30, 2018
    Publication date: May 30, 2019
    Inventors: CHIH-LIANG CHEN, LEI-CHUN CHOU, JACK LIU, KAM-TOU SIO, HUI-TING YANG, WEI-CHENG LIN, CHUN-HUNG LIOU, JIANN-TYNG TZENG, CHEW-YUEN YOUNG
  • Patent number: 10300104
    Abstract: The present disclosure provides various molecular constructs having a targeting element and an effector element. Methods for treating various diseases using such molecular constructs are also disclosed.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 28, 2019
    Assignee: IMMUNWORK INC.
    Inventors: Tse-Wen Chang, Hsing-Mao Chu, Chun-Yu Lin, Wei-Ting Tian
  • Patent number: 10301538
    Abstract: The present invention provides a phosphor composition and light emitting device using the same. The phosphor composition includes a first phosphor and a second phosphor, the second phosphor includes Phellodendron extract, Phellodendron extract emits lights with wavelength from 450 nm to 750 nm as it is excited by lights with wavelength from 300 nm to 480 nm. The LED device using the phosphor composition could emit warm white lights with wavelength from 400 nm to 800 nm.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: May 28, 2019
    Assignee: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventors: Wei-Jen Liu, Kuei-Ting Hsu, Pin-Chun Lin, Ming-Hsiu Shiu
  • Patent number: 10297588
    Abstract: A semiconductor device includes at least one first gate strip, at least one second gate strip, at least one first conductive line and at least one first conductive via. An end surface of the at least one first gate strip and an end surface of the at least one second gate strip are opposite each other. The at least one first conductive line is over the at least one first gate strip and the at least one second gate strip and across the end surface of the at least one first gate strip and the end surface of the at least one second gate strip. The at least one first conductive via connects the at least one first conductive line and the at least one first gate strip.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Cheng Lin, Hui-Ting Yang, Shih-Wei Peng, Jiann-Tyng Tzeng, Charles Chew-Yuen Young, Chih-Ming Lai
  • Patent number: 10297579
    Abstract: A structure includes a first package and a second package. The second package is coupled to the first package by one or more connectors. Epoxy flux residue is disposed around the connectors and in contact with the connectors. A method includes providing a first package having first connector pads and providing a second package having corresponding second connector pads. Solder paste is printed on each of the first connector pads. Epoxy flux is printed on each of the solder paste. The first and second connector pads are aligned and the packages are pressed together. The solder paste is reflowed to connect the first connector pads to the second connector pads while leaving an epoxy flux residue around each of the connections.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wei-Yu Chen, Kuei-Wei Huang, Hsiu-Jen Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu, Hsuan-Ting Kuo
  • Publication number: 20190148262
    Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.
    Type: Application
    Filed: March 29, 2018
    Publication date: May 16, 2019
    Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
  • Publication number: 20190146159
    Abstract: An optical housing for high power fiber components includes an upper cover, a lower base, and two isolating members. The upper cover includes a light-reflecting portion for containing the optical fiber and receiving and reflecting the light therefrom. The lower base is connected with the upper cover and includes a light-receiving portion which corresponds to the light-reflecting portion in position and surrounds the optical fiber, thereby receives the light from the light-reflecting portion. The isolating members are disposed between the upper cover and the lower base and located on two sides of the optical housing to prevent the leakage of light from the optical fiber.
    Type: Application
    Filed: August 27, 2018
    Publication date: May 16, 2019
    Inventors: CHIANG-HSIN LIN, WEI-TING LIN, JIAN-HUNG LIN, PO-TSE TAI, WEI-CHUNG YEN
  • Publication number: 20190148366
    Abstract: A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.
    Type: Application
    Filed: March 30, 2018
    Publication date: May 16, 2019
    Inventors: Wei-Chih WEN, Han-Ting TSAI, Chung-Te LIN
  • Publication number: 20190122946
    Abstract: Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: Shih-Yen Lin, Yu-Chih Liu, Chin-Liang Chen, Wei-Ting Lin, Kuan-Lin Ho
  • Patent number: 10269668
    Abstract: Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yen Lin, Yu-Chih Liu, Chin-Liang Chen, Wei-Ting Lin, Kuan-Lin Ho