Patents by Inventor Wei-Ting Lin
Wei-Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11552054Abstract: A package structure includes a semiconductor device, a circuit substrate and a heat dissipating lid. The semiconductor device includes a semiconductor die. The circuit substrate is bonded to and electrically coupled to the semiconductor device. The heat dissipating lid is bonded to the circuit substrate and thermally coupled to the semiconductor device, where the semiconductor device is located in a space confined by the heat dissipating lid and the circuit substrate. The heat dissipating lid includes a cover portion and a flange portion bonded to a periphery of the cover portion. The cover portion has a first surface and a second surface opposite to the first surface, where the cover portion includes a recess therein, the recess has an opening at the second surface, and a thickness of the recess is less than a thickness of the cover portion, where the recess is part of the space.Type: GrantFiled: June 29, 2020Date of Patent: January 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Ting Lin, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
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Patent number: 11417643Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.Type: GrantFiled: November 5, 2019Date of Patent: August 16, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Chin-Liang Chen, Jing Ruei Lu
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Patent number: 11277168Abstract: A communication device is disclosed. The communication device includes a transceiver circuit, an echo canceler, and a processor. The transceiver circuit is configured to transmit a test signal to a channel. The echo canceler is configured to obtain a plurality of echo power of a reflected signal corresponding to the test signal. The processor is configured to obtain a plurality of positions on the channel according to a parameter value. The parameter value is N, a number of the plurality of positions is N, and the plurality of positions corresponds to the top N largest of the plurality of echo power. The echo canceler is further configured to eliminate part of the plurality of echo power corresponding to the plurality of positions according to the plurality of positions.Type: GrantFiled: September 8, 2020Date of Patent: March 15, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Wei-Ting Lin, Yuan-Jih Chu, Li-Chung Chen, Hsin-Yun Hu
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Publication number: 20210407963Abstract: A package structure includes a semiconductor device, a circuit substrate and a heat dissipating lid. The semiconductor device includes a semiconductor die. The circuit substrate is bonded to and electrically coupled to the semiconductor device. The heat dissipating lid is bonded to the circuit substrate and thermally coupled to the semiconductor device, where the semiconductor device is located in a space confined by the heat dissipating lid and the circuit substrate. The heat dissipating lid includes a cover portion and a flange portion bonded to a periphery of the cover portion. The cover portion has a first surface and a second surface opposite to the first surface, where the cover portion includes a recess therein, the recess has an opening at the second surface, and a thickness of the recess is less than a thickness of the cover portion, where the recess is part of the space.Type: ApplicationFiled: June 29, 2020Publication date: December 30, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Ting Lin, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
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Patent number: 11211339Abstract: A semiconductor device includes a semiconductor die having an insulative layer and a conductive feature in the insulative layer, and a shield in contact with a lateral surface of the conductive feature. In some embodiments, the lateral surface of the conductive feature is aligned with an edge of the insulating material.Type: GrantFiled: December 4, 2019Date of Patent: December 28, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chuei-Tang Wang, Vincent Chen, Tzu-Chun Tang, Chen-Hua Yu, Ching-Feng Yang, Ming-Kai Liu, Yen-Ping Wang, Kai-Chiang Wu, Shou Zen Chang, Wei-Ting Lin, Chun-Lin Lu
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Patent number: 11121261Abstract: A semiconductor substrate includes a substrate, a first metal oxide semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a second metal oxide semiconductor layer. The first transistor includes a first metal oxide semiconductor pattern of the first metal oxide semiconductor layer, a first gate of the first conductive layer, a first source of the second conductive layer, and a first drain of the second conductive layer. The second transistor includes a second metal oxide semiconductor pattern of the first metal oxide semiconductor layer, a second gate of the first conductive layer, a second source of the second conductive layer, a second drain of the second conductive layer, and a third metal oxide semiconductor pattern of the second metal oxide semiconductor layer.Type: GrantFiled: February 5, 2020Date of Patent: September 14, 2021Assignee: Au Optronics CorporationInventors: Wei-Ting Lin, Dean Wang, Chun-Cheng Cheng
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Publication number: 20210175924Abstract: A communication device is disclosed. The communication device includes a transceiver circuit, an echo canceler, and a processor. The transceiver circuit is configured to transmit a test signal to a channel. The echo canceler is configured to obtain a plurality of echo power of a reflected signal corresponding to the test signal. The processor is configured to obtain a plurality of positions on the channel according to a parameter value. The parameter value is N, a number of the plurality of positions is N, and the plurality of positions corresponds to the top N largest of the plurality of echo power. The echo canceler is further configured to eliminate part of the plurality of echo power corresponding to the plurality of positions according to the plurality of positions.Type: ApplicationFiled: September 8, 2020Publication date: June 10, 2021Inventors: Wei-Ting LIN, Yuan-Jih CHU, Li-Chung CHEN, Hsin-Yun HU
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Patent number: 11031496Abstract: A MOSFET includes a substrate, a trench, a bottom oxide, a shield poly, two gate polys and an inter-poly oxide. The trench is formed on the substrate. The bottom oxide is formed on the trench. The shield poly is formed on the trench, and a part of the bottom oxide is separated by the shield poly. The two gate polys are formed on the bottom oxide. The inter-poly oxide is formed between the two gate polys. The shield poly is staggered from at least one of the two gate polys in a horizontal direction and a vertical direction. Therefore, the capacitance between a source electrode and a gate electrode is effectively reduced, and the delay time during switching is shorten and the energy loss is reduced at the same time.Type: GrantFiled: August 21, 2019Date of Patent: June 8, 2021Assignee: MOSEL VITELIC INC.Inventors: Wei-Ting Lin, Chun-Sheng Chen
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Patent number: 10900518Abstract: A linear guide apparatus may include a guide rail, a carriage block, at least two recirculating tubes, and two end covers. The carriage block has an axial sliding channel formed at a middle portion of a bottom surface thereof, and the carriage block is slidably coupled on the guide rail through the sliding channel. Each of two sides of the sliding channel has at least a sliding groove formed between the carriage block and guide rail. Each sliding groove comprises a plurality of rolling balls installed therein so as to enable the carriage block to slide forward and backward on the guide rail. Each of the sliding grooves is cooperated with a recirculating channel axially penetrating through the carriage block. Each of the recirculating tubes comprises a plurality of spiral threads to enable the rolling balls to have lateral roll at a specific angle when passing therethrough.Type: GrantFiled: June 20, 2019Date of Patent: January 26, 2021Inventor: Wei-Ting Lin
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Publication number: 20210005750Abstract: A semiconductor substrate includes a substrate, a first metal oxide semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a second metal oxide semiconductor layer. The first transistor includes a first metal oxide semiconductor pattern of the first metal oxide semiconductor layer, a first gate of the first conductive layer, a first source of the second conductive layer, and a first drain of the second conductive layer. The second transistor includes a second metal oxide semiconductor pattern of the first metal oxide semiconductor layer, a second gate of the first conductive layer, a second source of the second conductive layer, a second drain of the second conductive layer, and a third metal oxide semiconductor pattern of the second metal oxide semiconductor layer.Type: ApplicationFiled: February 5, 2020Publication date: January 7, 2021Applicant: Au Optronics CorporationInventors: Wei-Ting Lin, Dean Wang, Chun-Cheng Cheng
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Patent number: 10879140Abstract: Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.Type: GrantFiled: December 20, 2018Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yen Lin, Yu-Chih Liu, Chin-Liang Chen, Wei-Ting Lin, Kuan-Lin Ho
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Publication number: 20200400189Abstract: A linear guide apparatus may include a guide rail, a carriage block, at least two recirculating tubes, and two end covers. The carriage block has an axial sliding channel formed at a middle portion of a bottom surface thereof, and the carriage block is slidably coupled on the guide rail through the sliding channel. Each of two sides of the sliding channel has at least a sliding groove formed between the carriage block and guide rail. Each sliding groove comprises a plurality of rolling balls installed therein so as to enable the carriage block to slide forward and backward on the guide rail. Each of the sliding grooves is cooperated with a recirculating channel axially penetrating through the carriage block. Each of the recirculating tubes comprises a plurality of spiral threads to enable the rolling balls to have lateral roll at a specific angle when passing therethrough.Type: ApplicationFiled: June 20, 2019Publication date: December 24, 2020Inventor: Wei-Ting Lin
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Patent number: 10867835Abstract: A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.Type: GrantFiled: December 17, 2018Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lin Ho, Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Shih-Yen Lin
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Publication number: 20200357659Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: SHOU ZEN CHANG, CHUN-LIN LU, KAI-CHIANG WU, CHING-FENG YANG, VINCENT CHEN, CHUEI-TANG WANG, YEN-PING WANG, HSIEN-WEI CHEN, WEI-TING LIN
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Publication number: 20200328302Abstract: A MOSFET includes a substrate, a trench, a bottom oxide, a shield poly, two gate polys and an inter-poly oxide. The trench is formed on the substrate. The bottom oxide is formed on the trench. The shield poly is formed on the trench, and a part of the bottom oxide is separated by the shield poly. The two gate polys are formed on the bottom oxide. The inter-poly oxide is formed between the two gate polys. The shield poly is staggered from at least one of the two gate polys in a horizontal direction and a vertical direction. Therefore, the capacitance between a source electrode and a gate electrode is effectively reduced, and the delay time during switching is shorten and the energy loss is reduced at the same time.Type: ApplicationFiled: August 21, 2019Publication date: October 15, 2020Inventors: Wei-Ting Lin, Chun-Sheng Chen
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Publication number: 20200286748Abstract: A lid attach process includes dipping a periphery of a lid in a dipping tank of adhesive material such that the adhesive material attaches to the periphery of the lid. The lid attach process further includes positioning the lid over a die attached to a substrate using a lid carrier, wherein the periphery of the lid is aligned with a periphery of the lid carrier. The lid attach process further includes attaching the lid to the substrate with the adhesive material forming an interface with the substrate. The lid attach process further includes contacting a thermal interface material (TIM) on the die with the lid.Type: ApplicationFiled: May 22, 2020Publication date: September 10, 2020Inventors: Chin-Liang CHEN, Wei-Ting LIN, Yu-Chih LIU, Kuan-Lin HO, Jason SHEN
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Patent number: 10727082Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electric Magnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.Type: GrantFiled: August 28, 2015Date of Patent: July 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shou Zen Chang, Chun-Lin Lu, Kai-Chiang Wu, Ching-Feng Yang, Vincent Chen, Chuei-Tang Wang, Yen-Ping Wang, Hsien-Wei Chen, Wei-Ting Lin
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Patent number: 10685853Abstract: A lid attach process includes providing a substrate and a die attached to the substrate, providing a lid and dipping a periphery of the lid in a dipping tank of adhesive material such that the adhesive material attaches to the periphery of the lid, and positioning the lid over the die and placing the lid on a top of the substrate with the adhesive material being adapted to interface with a periphery of the substrate.Type: GrantFiled: November 2, 2016Date of Patent: June 16, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Kuan-Lin Ho, Jason Shen
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Publication number: 20200111753Abstract: A semiconductor device includes a semiconductor die having an insulative layer and a conductive feature in the insulative layer, and a shield in contact with a lateral surface of the conductive feature. In some embodiments, the lateral surface of the conductive feature is aligned with an edge of the insulating material.Type: ApplicationFiled: December 4, 2019Publication date: April 9, 2020Inventors: CHUEI-TANG WANG, VINCENT CHEN, TZU-CHUN TANG, CHEN-HUA YU, CHING-FENG YANG, MING-KAI LIU, YEN-PING WANG, KAI-CHIANG WU, SHOU ZEN CHANG, WEI-TING LIN, CHUN-LIN LU
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Publication number: 20200066704Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.Type: ApplicationFiled: November 5, 2019Publication date: February 27, 2020Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Chin-Liang Chen, Jing Ruei Lu