Patents by Inventor Wei-Ting Lin

Wei-Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9553062
    Abstract: A fingerprint identification device includes a first dielectric layer, a fingerprint sensing chip, a packaging layer, a first redistribution layer, a second dielectric layer, a second redistribution layer, and a third dielectric layer. The fingerprint sensing chip is disposed on the first dielectric layer and has a sensing transmission pad. The packaging layer defines a first via hole and covers the first dielectric layer and fingerprint sensing chip. Disposed on the packaging layer, the first redistribution layer contacts a drive transmission pad via the first via hole. The second dielectric layer defines a second via hole and covers the packaging layer and the first redistribution layer. Disposed on the second dielectric layer, the second redistribution layer defines a looped pattern, in addition to connect electrically with the first redistribution layer via the second via hole. The third dielectric layer covers the second dielectric layer and second redistribution layer.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: January 24, 2017
    Assignee: J-METRICS TECHNOLOGY CO., LTD.
    Inventors: Chen-Chih Fan, Wei-Ting Lin, Shih-Chun Kuo
  • Publication number: 20170013111
    Abstract: An intelligent notification device is provided. The intelligent notification device is adapted to communicate with at least one electronic device. The intelligent notification device includes a detecting device and a controller. The detecting device detects a status parameter of at least one user and an enviromental parameter of the electronic device. The controller is electrically connected to the detecting device to control the electronic device to notify one of a plurality of events in an event schedule according to the event schedule and to dynamically adjust a time sequency of the events in the event schedule according to at least one of the enviromental parameter and the status parameter. An intelligent notification method is further provided.
    Type: Application
    Filed: July 7, 2016
    Publication date: January 12, 2017
    Inventors: Min-Che Huang, Kuo-Chung Chiu, Hsiao-Kai Li, Chia-Hsin Yang, Tsung-Han Tsai, Wei-Chi Yen, Shih-Hao Ke, Shu-Hui Chou, Wei-Ting Lin, Wen-Chieh Tseng, Ting-Yu Chen, Shuan-Yi Chu
  • Publication number: 20160353257
    Abstract: An automatic notification device for communicating with a plurality of electronic device is provided. The automatic notification device includes a controller. The controller determines whether to transfer information to the first electronic device according to a utilizing status of the first electronic device, and receives a determine signal from the first electronic device to determine whether the information transferred to the first electronic device has already been read according to the determine signal. Furthermore, an automatic notification method applied to the automatic notification device is also provided.
    Type: Application
    Filed: May 18, 2016
    Publication date: December 1, 2016
    Inventors: Min-Che Huang, Kuo-Chung Chiu, Hsiao-Kai Li, Chia-Hsin Yang, Tsung-Han Tsai, Wei-Chi Yen, Shih-Hao Ke, Shu-Hui Chou, Wei-Ting Lin, Wen-Chieh Tseng, Ting-Yu Chen, Shuan-Yi Chu
  • Patent number: 9501593
    Abstract: A semiconductor device design method includes generating a layout of a semiconductor device based on schematic data. The layout includes location data for at least one electrical component. The method includes receiving first voltage data associated with at least one electrical component. The method includes receiving second voltage data based on simulation results for the semiconductor device. The method includes incorporating, based on the location data of the at least one electrical component, the first voltage data or the second voltage data in the layout to generate a modified layout. The first voltage data or the second voltage data being incorporated in at least one marker layer of the modified layout. The method includes performing a voltage-dependent design rule check (VDRC) on the modified layout. The VDRC analyzes spacing rules associated with the at least one electrical component based on the first voltage data or the second voltage data.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: November 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mu-Jen Huang, Chih Chi Hsiao, Wei-Ting Lin, Tsung-Hsin Yu, Chien-Wen Chen, Yung-Chow Peng
  • Patent number: 9502373
    Abstract: An adhesive dispenser comprises a dispensing head. The dispensing head comprises an adhesive material applicator portion on a first level of the dispensing head. The adhesive material applicator portion corresponds to a periphery of a package. The dispensing head also comprises a thermal interface material (TIM) applicator portion on a second level of the dispensing head different from the first level. The TIM applicator portion corresponds to a die of the package. The dispensing head further comprises an adhesive material conduit configured to supply the adhesive material applicator portion with an adhesive material. The dispensing head additionally comprises a TIM conduit configured to supply the TIM applicator portion with a TIM.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: November 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Kuan-Lin Ho, Jason Shen
  • Patent number: 9486080
    Abstract: A body-shaping support structure includes a main body and a flexible body. The main body includes a shaping section. The shaping section is in a concave configuration. The main body has at least a portion including an elastic material and forming at least one adjustment gap to form a branch section and an adjustment section. The branch section is elastically deformable for adjustment. The flexible body is set to extend through and interlace the branch section and the adjustment section. The branch section is deformable and movable to achieve adjustment of the size of the shaping section. The flexible body connects the branch section and the adjustment section to each other so as to maintain effective fixation of the shaping section without changing the shape. The shaping section can receive a predetermined human body portion to be positioned thereon to enhance an effect of supporting and shaping the human body.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: November 8, 2016
    Inventor: Wei-Ting Lin
  • Publication number: 20160275333
    Abstract: A suspended capacitive fingerprint sensor includes a substrate, capacitive sensing units disposed on the substrate and one or more insulation protection layer. Each of the capacitive sensing units includes a fixed electrode, a suspended electrode, and a chamber between the fixed electrode and the suspended electrode. The insulation protection layer covers the capacitive sensing units, so that the capacitive sensing units sense a fingerprint of a finger above the insulation protection layer. A method for manufacturing the suspended capacitive fingerprint sensor is also provided.
    Type: Application
    Filed: February 16, 2016
    Publication date: September 22, 2016
    Inventor: Wei-Ting Lin
  • Publication number: 20160278005
    Abstract: A data transmission system includes a device and a base. The base includes a near field communication (NFC) module and a processing module configured to determine whether a wireless network exits. The NFC module includes a determining unit configured to determine whether the NFC module writes a predetermined tag after the processing module determines the wireless network exits and configured to determine whether the predetermined tag is an authorization code, a sending unit configured to send a service set identifier (SSID) and a password to the device after the predetermined tag is the authorization code, and a control unit configured to switch an input mode of the base to a wireless network mode after the SSID and the password are sent to the device. The device is configured to be connected to the wireless network after receiving the SSID and the password. A communication method is also provided.
    Type: Application
    Filed: May 19, 2015
    Publication date: September 22, 2016
    Inventors: CHI-KANG CHIANG, WEI-TING LIN, RU-ME NA JIANG, AI-GUO CHENG, KO-YI LEE, PING-CHUAN TSAI, JING-HU SONG, SHUO-HSIU CHANG
  • Patent number: 9415501
    Abstract: An apparatus for manufacturing a semiconductor device includes a holder for holding a carrier and a supporting base for receiving the holder comprising a recess for accommodating a plurality of balls mounted on a surface of the carrier. Furthermore, a method of manufacturing a semiconductor device includes providing a carrier, providing an apparatus comprising a supporting base including a recess, holding the carrier on the supporting base and accommodating a plurality of balls mounted on a surface of the carrier in the recess.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Shih-Yen Lin
  • Publication number: 20160224775
    Abstract: An electronic apparatus includes a fingerprint sensor and an operation unit. The fingerprint sensor senses fingerprint images of a finger at different time instants. In a vector mode, the operation unit determines one or multiple moving directions of the finger according to the fingerprint images to generate a motion vector signal. The electronic apparatus executes a specific function according to the motion vector signal. The specific function is selected from a group consisting of a homepage key function, a function key function, and an unlocking function.
    Type: Application
    Filed: January 22, 2016
    Publication date: August 4, 2016
    Inventor: Wei-Ting Lin
  • Patent number: 9391235
    Abstract: A patterned substrate for epitaxially growing a semiconductor material includes: a top surface; and a plurality of spaced apart recesses, each of which is indented downwardly from the top surface and is defined by n crystal planes, n being an integer not less than 3. Each of the crystal planes has an upper edge meeting the top surface and is adapted for epitaxially growing the semiconductor material. A maximum distance from one of the upper edges of one of the recesses to an adjacent one of the upper edges of an adjacent one of the recesses is not greater than 500 nm.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: July 12, 2016
    Assignee: NATIONAL CHUNG-HSING UNIVERSITY
    Inventors: Dong-Sing Wuu, Ray-Hua Horng, Wei-Ting Lin
  • Publication number: 20160186012
    Abstract: A thermally conductive, electrically insulating, high temperature resistant and flame retardant adhesive sheet includes a substrate, an adhesive layer disposed on the substrate, metal hydroxide and metal oxide. The adhesive layer is formed from an adhesive composition, which is made of from 10 to 90 wt. % of a solvent-free and pressure sensitive siloxane resin. The siloxane resin includes hydrophilic functional groups, and the weight percentage of the hydrophilic functional groups in the siloxane resin is in the range of 1 to 10 wt.
    Type: Application
    Filed: March 10, 2016
    Publication date: June 30, 2016
    Inventors: Yong-Qi Cai, Yuan-Shun Tsai, Wei-Ting Lin
  • Publication number: 20160188776
    Abstract: A semiconductor device design method includes generating a layout of a semiconductor device based on schematic data. The layout includes location data for at least one electrical component. The method includes receiving first voltage data associated with at least one electrical component. The method includes receiving second voltage data based on simulation results for the semiconductor device. The method includes incorporating, based on the location data of the at least one electrical component, the first voltage data or the second voltage data in the layout to generate a modified layout. The first voltage data or the second voltage data being incorporated in at least one marker layer of the modified layout. The method includes performing a voltage-dependent design rule check (VDRC) on the modified layout. The VDRC analyzes spacing rules associated with the at least one electrical component based on the first voltage data or the second voltage data.
    Type: Application
    Filed: March 9, 2016
    Publication date: June 30, 2016
    Inventors: Mu-Jen HUANG, Chih Chi HSIAO, Wei-Ting LIN, Tsung-Hsin YU, Chien-Wen CHEN, Yung-Chow PENG
  • Patent number: 9310946
    Abstract: A capacitive-type touch control display includes: a rear plate including a first polarizer sheet and a TFT array layer; a front plate including a color filter layer, a second polarizer sheet, an adhesive layer, a transparent touch sensor layer adhesively bonded to the second polarizer sheet through the adhesive layer, and a transparent hard coating layer formed on the touch sensor layer; a liquid crystal cell; and a housing including a main body and an end flange. The main body has an open end. The end flange extends inwardly and transversely from the open end, and defines a front window that exposes a touch sensing region of the touch sensor layer underneath the hard coating layer. The end flange covers a peripheral region of the touch sensor layer.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: April 12, 2016
    Assignee: Top Victory Investments Limited
    Inventors: Wei-Ting Lin, Yung-Shin Liou
  • Patent number: 9305134
    Abstract: A semiconductor device design method includes extracting voltage data associated with at least one electrical component in a layout of a semiconductor device and based on a result of a simulation of an operation of the semiconductor device. Based on location data of the at least one electrical component, the extracted voltage data is incorporated in the layout to generate a modified layout of the semiconductor device. One or more operations of the method are performed by at least one processor.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: April 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mu-Jen Huang, Chih Chi Hsiao, Wei-Ting Lin, Tsung-Hsin Yu, Chien-Wen Chen, Yung-Chow Peng
  • Patent number: 9287233
    Abstract: The present disclosure relates to an integrated chip package having a plurality of different adhesive layers that provide for a low lid induced stress good warpage control of a substrate and/or IC die, and an associated method of formation. The integrated chip package has an integrated chip (IC) die coupled to an underlying substrate by an electrically conductive interconnect structure. A first adhesive layer, having a first Young's modulus, is disposed onto the substrate at a first plurality of positions surrounding the IC die. A second adhesive layer, having a second Young's modulus different than the first Young's modulus, is disposed onto the substrate at a second plurality of positions surrounding the IC die. A lid is affixed to the substrate by the first and second adhesive layers and extends to a position overlying the IC die.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Liang Chen, Wei-Ting Lin, Kuan-Lin Ho, Yu-Chih Liu, Chun-Cheng Lin, Shih-Yen Lin
  • Publication number: 20160071744
    Abstract: Some embodiments of the present disclosure provide a method of manufacturing a device. The method includes providing a carrier, the carrier including a top surface, covering a portion of the top surface with a plurality of active dies, disposing a protrudent band over a periphery of the carrier, wherein the protrudent band includes a rim shaped along the contour of the carrier, and forming a molding compound over the carrier to cover the plurality of active dies. A method for determining a width of the protrudent band of a device described herein is also provided.
    Type: Application
    Filed: November 10, 2015
    Publication date: March 10, 2016
    Inventors: YU-CHIH LIU, CHANG-CHIA HUANG, SHIH-YEN LIN, CHIN-LIANG CHEN, KUAN-LIN HO, WEI-TING LIN
  • Patent number: 9278512
    Abstract: A substrate bonding and debonding method includes the steps of: providing a substrate; forming a first silicone glue layer on a peel-off region of the substrate and a second silicone glue layer on a peripheral region of the substrate, in which the first and second silicone glue layers contain the same silicone main agent and silicone curing agent in a different ratio; adhering an opposite substrate to the first and second silicone glue layers; curing the first and second silicone glue layers to bond the substrate to the opposite substrate; and separating a portion of the substrate from the opposite substrate.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: March 8, 2016
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Shuo-Yang Sun, Wan-Chen Huang, Wei-Ting Lin, Chun-Cheng Cheng
  • Publication number: 20150357318
    Abstract: Chip packages and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a chip package includes: stacking a second chip on a first chip, wherein a first interconnect including a support structure and a bonding structure is disposed between the first chip and the second chip; bonding the first chip and the second chip via a thermal process applied to the bonding structure of the first interconnect; stacking a third chip on the second chip, wherein a second interconnect including a support structure and a bonding structure is disposed between the second chip and the third chip; bonding the second chip and the third chip via the thermal process applied to the bonding structure of the second interconnect; and reflowing the bond between the first and second chips and simultaneously reflowing the bond between the second and third chips.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 10, 2015
    Inventors: Chin-Liang Chen, Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Shih-Yen Lin
  • Publication number: 20150357309
    Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 10, 2015
    Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Chin-Liang Chen, Jing Ruei Lu