Patents by Inventor Wei-Ting Lin

Wei-Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10043761
    Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electromagnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chuei-Tang Wang, Vincent Chen, Tzu-Chun Tang, Chen-Hua Yu, Ching-Feng Yang, Ming-Kai Liu, Yen-Ping Wang, Kai-Chiang Wu, Shou Zen Chang, Wei-Ting Lin, Chun-Lin Lu
  • Publication number: 20180184086
    Abstract: Encoding or decoding blocks of video frames using multiple reference frames with adaptive temporal filtering can include generating one or more candidate reference frames by applying temporal filtering to one or more frames of a video sequence according to relationships between respective ones of the one or more frames and a current frame of the video sequence. A reference frame to use for predicting the current frame can be selected from the one or more candidate reference frames, and a prediction block can be generated using the selected reference frame. During an encoding operation, the prediction block can be used to encode a block of a current frame of the video sequence. During a decoding operation, the prediction block can be used to decode a block of a current frame of the video sequence.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Debargha Mukherjee, Yaowu Xu, James Bankoski, Paul Wilkins, Jingning Han, Yuxin Liu, Wei-Ting Lin
  • Publication number: 20180122791
    Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 3, 2018
    Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Chin-Liang Chen, Jing Ruei Lu
  • Publication number: 20180062477
    Abstract: The servo motor includes a casing, a stator, a rotor and a circuit board. The casing has a hollow body, a first bearing and a second bearing. The hollow body is mounted between the first bearing and the second bearing. The stator is disposed inside the hollow body, and surrounds an axial hollow portion. The rotor is disposed inside the stator. A shaft passes through the rotor in an axial direction, and two ends of the shaft are respectively mounted on the first bearing and the second bearing. The circuit board is disposed inside the hollow body and interposed between the stator and the first bearing, the periphery of the circuit board has a plurality of solder pads electrically connected to the stator. An outer surface of the circuit board has a protection layer, which covers the region of the solder pads near the outer edge of the periphery.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 1, 2018
    Inventors: Wei-Min Tsao, Chun-Lung Ho, Wei-Ting Lin
  • Patent number: 9893043
    Abstract: Chip packages and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a chip package includes: stacking a second chip on a first chip, wherein a first interconnect including a support structure and a bonding structure is disposed between the first chip and the second chip; bonding the first chip and the second chip via a thermal process applied to the bonding structure of the first interconnect; stacking a third chip on the second chip, wherein a second interconnect including a support structure and a bonding structure is disposed between the second chip and the third chip; bonding the second chip and the third chip via the thermal process applied to the bonding structure of the second interconnect; and reflowing the bond between the first and second chips and simultaneously reflowing the bond between the second and third chips.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Liang Chen, Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Shih-Yen Lin
  • Patent number: 9887144
    Abstract: A ring structure for chip packaging comprises a frame portion adaptable to bond to a substrate and at least one corner portion. The frame portion surrounds a semiconductor chip and defines an inside opening, and the inside opening exposes a portion of a surface of the substrate. The at least one corner portion extends from a corner of the frame portion toward the chip, and the corner portion is free of a sharp corner.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: February 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Yi Lin, Yu-Chih Liu, Ming-Chih Yew, Tsung-Shu Lin, Bor-Rung Su, Jing Ruei Lu, Wei-Ting Lin
  • Publication number: 20180033775
    Abstract: A method includes bonding a first device die onto a top surface of a package substrate, and performing an expose molding on the first device die and the package substrate. At least a lower portion of the first device die is molded in a molding material. A top surface of the molding material is level with or higher than a top surface of the first device die. After the expose molding, a second device die is bonded onto a top surface of the first device die. The second device die is electrically coupled to the first device die through through-silicon vias in a semiconductor substrate of the first device die.
    Type: Application
    Filed: October 6, 2017
    Publication date: February 1, 2018
    Inventors: Yu-Chih Liu, Hai-Ming Chen, Wei-Ting Lin, Jing Ruei Lu, Tsung-Ding Wang
  • Patent number: 9859265
    Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Chin-Liang Chen, Jing Ruei Lu
  • Publication number: 20170345708
    Abstract: A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.
    Type: Application
    Filed: August 14, 2017
    Publication date: November 30, 2017
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Shih-Yen Lin
  • Publication number: 20170345201
    Abstract: An animation display system is provided. The animation display system includes a display; a storage configured to store a language model database, a phonetic-symbol lip-motion matching database and a lip motion synthesis database; and a processor electronically connected to the storage and the display, respectively. The processor includes a speech conversion module, a phonetic-symbol lip-motion matching module, and a lip motion synthesis module. A lip animation display method is also provided.
    Type: Application
    Filed: May 24, 2017
    Publication date: November 30, 2017
    Inventors: Wei-Ting LIN, Tsung-Yu HOU, Min-Che HUANG, Shih-Hao KE, Shu-Hui CHOU
  • Patent number: 9805997
    Abstract: Packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling a ring to a substrate, and coupling an integrated circuit die to the substrate within the ring. A molding material is disposed around the integrated circuit die within the ring.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Liu, Chien-Kuo Chang, Wei-Ting Lin, Kuan-Lin Ho, Chin-Liang Chen, Shih-Yen Lin
  • Patent number: 9793242
    Abstract: A method includes bonding a first device die onto a top surface of a package substrate, and performing an expose molding on the first device die and the package substrate. At least a lower portion of the first device die is molded in a molding material. A top surface of the molding material is level with or higher than a top surface of the first device die. After the expose molding, a second device die is bonded onto a top surface of the first device die. The second device die is electrically coupled to the first device die through through-silicon vias in a semiconductor substrate of the first device die.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Liu, Hai-Ming Chen, Wei-Ting Lin, Jing Ruei Lu, Tsung-Ding Wang
  • Patent number: 9786520
    Abstract: Some embodiments of the present disclosure provide a method of manufacturing a device. The method includes providing a carrier, the carrier including a top surface, covering a portion of the top surface with a plurality of active dies, disposing a protrudent band over a periphery of the carrier, wherein the protrudent band includes a rim shaped along the contour of the carrier, and forming a molding compound over the carrier to cover the plurality of active dies. A method for determining a width of the protrudent band of a device described herein is also provided.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: October 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Chih Liu, Chang-Chia Huang, Shih-Yen Lin, Chin-Liang Chen, Kuan-Lin Ho, Wei-Ting Lin
  • Publication number: 20170271223
    Abstract: Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Shih-Yen Lin, Yu-Chih Liu, Chin-Liang Chen, Wei-Ting Lin, Kuan-Lin Ho
  • Patent number: 9735043
    Abstract: A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Shih-Yen Lin
  • Patent number: 9684811
    Abstract: A suspended capacitive fingerprint sensor includes a substrate, capacitive sensing units disposed on the substrate and one or more insulation protection layer. Each of the capacitive sensing units includes a fixed electrode, a suspended electrode, and a chamber between the fixed electrode and the suspended electrode. The insulation protection layer covers the capacitive sensing units, so that the capacitive sensing units sense a fingerprint of a finger above the insulation protection layer. A method for manufacturing the suspended capacitive fingerprint sensor is also provided.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: June 20, 2017
    Assignee: J-METRICS TECHNOLOGY CO., LTD.
    Inventor: Wei-Ting Lin
  • Patent number: 9679188
    Abstract: A fingerprint sensor packaging module includes a light-pervious cover layer, a conductive pattern layer on the light-pervious cover layer, a finger sensing chip on the conductive pattern layer, a circuit board on the light-pervious cover layer, and a package member. The conductive pattern layer includes a plurality of pads. The fingerprint sensing chip is electrically connected to the conductive pattern layer by contacting to the pads. The circuit board is electrically connected to the conductive pattern layer and has a hole and the hole exposes the fingerprint sensing chip. The fingerprint sensing chip is disposed in the hole. The package member disposed in the hole and at least cover the fingerprint sensing chip.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: June 13, 2017
    Assignee: J-METRICS TECHNOLOGY CO., LTD.
    Inventor: Wei-Ting Lin
  • Patent number: 9673119
    Abstract: Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yen Lin, Yu-Chih Liu, Chin-Liang Chen, Wei-Ting Lin, Kuan-Lin Ho
  • Patent number: 9661794
    Abstract: A method of manufacturing a package structure includes at least the following steps. A wafer is provided. A flux layer is applied onto at least part of the wafer. A stencil is provided over the wafer. The stencil includes a plurality of apertures exposing the flux layer. A dispenser is provided over the stencil. A plurality of SMDs are fed over the stencil with the dispenser. The dispenser is moved to drive the SMDs into the apertures of the stencil. The stencil is removed and the flux layer is reflowed.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shou-Zen Chang, Chen-Hua Yu, Chung-Shi Liu, Kai-Chiang Wu, Wei-Ting Lin
  • Publication number: 20170141593
    Abstract: The present disclosure provides a power saving device with power supply, comprising a charger power circuit, a receptacle, a plug detection unit, an ON/OFF control circuit and a power output enable circuit. The plug detection unit uses a mechanical or electrical detection apparatus to detect whether a plug-in device is inserted or not. When there is no plug-in device in the receptacle, the power output enable circuit will cut off the power to the charger power circuit. So the power consumption of the power saving device is reduced while no plug-in device is inserted into the receptacle.
    Type: Application
    Filed: April 21, 2016
    Publication date: May 18, 2017
    Inventors: WEN-SHENG CHEN, KUN-HUNG LEE, CHIH-TAI CHEN, HAN-JU CHIANG, BO-CHIH LIN, TSUNG-PO HSU, WEI-TING LIN