Patents by Inventor Wei Wang

Wei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240057572
    Abstract: The invention discloses methods for the generation of chimaeric human—non-human antibodies and chimaeric antibody chains, antibodies and antibody chains so produced, and derivatives thereof including fully humanised antibodies; compositions comprising said antibodies, antibody chains and derivatives, as well as cells, non-human mammals and vectors, suitable for use in said methods.
    Type: Application
    Filed: September 13, 2022
    Publication date: February 22, 2024
    Inventors: Allan Bradley, E-Chiang Lee, Qi Liang, Wei Wang
  • Publication number: 20240059619
    Abstract: A method for preparing an ecological foamed ceramic from lepidolite filter mud whole waste belongs to the field of environmental protection and resource reuse. The ecological foamed ceramic with excellent properties can be prepared by using lepidolite filter mud as the main raw materials, including ball milling, homogenization, drying, material distribution, and heat treatment. The amount of lepidolite filter mud in the present invention accounts for more than 90%, which is a whole waste utilization and can achieve high-value utilization of bulk lepidolite filter mud. The present invention uses a composite foaming agent combined with a foaming technology and has the advantages of rapid foaming and controllable pore size compared with a single foaming agent. The ecological foamed ceramic prepared by the present invention meets the industrial standard of CJ/T 299-2008 “Artificial ceramic filter material for water treatment” and has potential application value in domestic sewage treatment.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Applicant: BEIJING UNIVERSITY OF TECHNOLOGY
    Inventors: Dean PAN, Xiaoguang ZHANG, Ruhao KONG, Qijun ZHANG, Zhe TAN, Wei WANG
  • Publication number: 20240061455
    Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang HUANG, Yeh-Ning JOU, Ching-Ho LI, Kai-Chieh HSU, Chun-Chih CHEN, Chien-Wei WANG, Gong-Kai LIN, Li-Fan CHEN
  • Publication number: 20240062351
    Abstract: Provided is a method for evaluating video quality, an electronic device and a storage medium, relating to the field of computer technology, and in particular, to the field of artificial intelligence, cloud computing, computer vision and deep learning technologies. The method includes: determining a plurality of video frames containing a target object in a target video; obtaining HSL data of an image area corresponding to the target object in the plurality of video frames; and evaluating a quality of the target video according to the HSL data.
    Type: Application
    Filed: February 24, 2023
    Publication date: February 22, 2024
    Inventors: Wei WANG, Yizhuo LIU
  • Publication number: 20240062839
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a set of memory cells of a source management unit of the memory device to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a first threshold; responsive to determining that the data integrity metric value fails to satisfy the first threshold, determining whether the data integrity metric value satisfies a second threshold that is lower than the first threshold; responsive to determining that the data integrity metric value satisfies the second threshold, causing the memory device to copy data from the source management unit to a destination set of pages of the memory device; and performing a subsequent data integrity check on one or more invalid pages of the source management unit.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Inventors: Wei Wang, Seungjune Jeon, Yang Liu, Charles See Yeung Kwong
  • Publication number: 20240064950
    Abstract: A semiconductor device includes a first source/drain feature on a front side of a substrate. The device includes a first backside metal line under the first source/drain feature and extending lengthwise along a first direction. The device includes a first backside via disposed between the first source/drain feature and the first backside metal line. The first backside metal line is a first bit line of a first static random access memory (SRAM) cell and is connected to the first source/drain feature through the first backside via. The first backside metal line includes a first portion and a second portion each extending widthwise along a second direction perpendicular to the first direction, the first portion is wider than the second portion, and the first portion partially lands on the first backside via. The first and the second portions are substantially aligned on one side along the first direction.
    Type: Application
    Filed: August 18, 2022
    Publication date: February 22, 2024
    Inventors: Jui-Lin Chen, Kian-Long Lim, Feng-Ming Chang, Yi-Feng Ting, Hsin-Wen Su, Lien-Jung Hung, Ping-Wei Wang
  • Publication number: 20240059794
    Abstract: Provided are single domain antibodies that bind to GUCY2C, and chimeric antigen receptors comprising same. Further provided are engineered immune effector cells (such as T cells) comprising the chimeric antigen receptors. Pharmaceutical compositions, kits and methods of treating a disease or disorder are also provided.
    Type: Application
    Filed: December 16, 2021
    Publication date: February 22, 2024
    Applicant: PARASOL BIOTECH LTD.
    Inventors: Ling HE, Lin WANG, Wei WANG
  • Patent number: 11908699
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: February 20, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
  • Patent number: 11909956
    Abstract: Systems and methods for deep neural network (DNN)-based cross component prediction are provided. A method includes inputting a reconstructed luma block of an image or video into a DNN; and predicting, by the DNN, a reconstructed chroma block of the image or video based on the reconstructed luma block that is input. Luma and chroma reference information and side information may also be input into the DNN to predict the reconstructed chroma block. The various inputs may also be generated using processes such as downsampling and transformation.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: February 20, 2024
    Assignee: TENCENT AMERICA LLC
    Inventors: Sheng Lin, Wei Jiang, Wei Wang, Liqiang Wang, Shan Liu, Xiaozhong Xu
  • Patent number: 11908860
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Wen-Chun Keng, Chih-Chuan Yang, Shih-Hao Lin
  • Patent number: 11908103
    Abstract: There is included a method and apparatus comprising computer code configured to cause a processor or processors to perform obtaining an input low resolution (LR) image comprising a height, a width, and a number of channels, implementing a feature learning deep neural network (DNN) configured to compute a feature tensor based on the input LR image, generating, by an upscaling DNN, a high resolution (HR) image, having a higher resolution than the input LR image, based on the feature tensor computed by the feature learning DNN, wherein a networking structure of the upscaling DNN differs depending on different scale factors, and wherein a networking structure of the feature learning DNN is a same structure for each of the different scale factors.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: February 20, 2024
    Assignee: TENCENT AMERICA LLC
    Inventors: Wei Jiang, Wei Wang, Shan Liu
  • Patent number: 11908905
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
  • Patent number: 11910585
    Abstract: Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region, a WPU region, a first well extending lengthwise along a first direction through the circuit region and into the WPU region, a second well extending lengthwise along the first direction through the circuit region and into the WPU region, and a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chuan Yang, Chang-Ta Yang, Ping-Wei Wang
  • Patent number: 11897331
    Abstract: Sound signals that are not audible are generated by one or more speakers disposed in the vehicle. Reflected sound signals from a driver or a passenger of the vehicle that are not audible are received by one or more microphones disposed in the vehicle. A behavior-induced acoustic pattern is detected based on the reflected ultrasound signals. The behavior-induced acoustic pattern is analyzed to recognize a behavior of the driver or the passenger of the vehicle. A response or an alert is generated according to the recognized behavior of the driver or the passenger in the vehicle.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: February 13, 2024
    Assignee: BAIDU USA LLC
    Inventors: Wei Wang, Qi Luo, Kecheng Xu, Hongyi Sun, Wesley Reynolds, Zejun Lin
  • Patent number: 11900640
    Abstract: A method of substitutional neural residual compression is performed by at least one processor and includes estimating motion vectors, based on a current image frame and a previous reconstructed image frame, obtaining a predicted image frame, based on the estimated motion vectors and the previous reconstructed image frame, and subtracting the obtained predicted image frame from the current image frame to obtain a substitutional residual. The method further includes encoding the obtained substitutional residual, using a first neural network, to obtain an encoded representation, and compressing the encoded representation.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: February 13, 2024
    Assignee: TENCENT AMERICA LLC
    Inventors: Wei Jiang, Wei Wang, Shan Liu
  • Patent number: 11901496
    Abstract: A light-emitting module, a display module and a display device are provided. The light-emitting module includes multiple light-emitting elements, a micro lens array disposed on a light-emitting side of the multiple light-emitting elements, and a low-refractive material layer disposed on a side of the micro lens array away from the multiple light-emitting elements, wherein a refractive index of the low-refractive material layer is smaller than a refractive index of the micro lens array; light emitted by the light-emitting element may be processed by the micro lens array and the low-refractive material layer to form a dot matrix light source which irradiates multiple preset opening regions which are disposed at intervals.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: February 13, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Qiuyu Ling, Xianqin Meng, Wei Wang, Weiting Peng, Yujiao Guo, Yishan Tian, Xiaochuan Chen
  • Patent number: 11901184
    Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: February 13, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
  • Publication number: 20240045258
    Abstract: Embodiments of the present disclosure are directed to a display module and a display device. The display module includes a display panel and an optical film arranged on an eminent side of the display panel. The optical film includes a first pattern layer and a second pattern layer disposed on a surface of the first pattern layer away from the display panel. The first pattern layer includes a plurality of first protrusions and a plurality of first recesses away from the display panel. The second pattern layer includes a plurality of second protrusions and a plurality of second recesses near first pattern layer. A refractive index of the first pattern layer is greater than a refractive index of the second pattern layer.
    Type: Application
    Filed: March 4, 2022
    Publication date: February 8, 2024
    Applicant: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Wei WANG, Weiheng YANG, Gang LIU
  • Patent number: D1014942
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: February 20, 2024
    Assignee: HENAN BANGNI BIOLOGICAL ENGINEERING CO., LTD.
    Inventors: Ning Li, Wei Wang
  • Patent number: D1015329
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: February 20, 2024
    Assignee: Elo Touch Solutions, Inc.
    Inventors: David Noppenberger, Wei Wang, Xingdong Zhao, Hui Yang