Abstract: An array substrate includes a first substrate; and a first electrode and a second electrode disposed on the first substrate and located in a sub-pixel region. At least one of the first electrode and the second electrode includes a plurality of electrode strips. Every two adjacent electrode strips in the first electrode and the second electrode have a slit therebetween. The slit includes a first end portion, a straight portion, and a second end portion connected in sequence. A bend is formed at a connection position of the first end portion and the straight portion, and the second end portion is formed by protruding from the straight portion. The straight portion includes a first edge and a second edge parallel to each other, and an average width of the first end portion in a direction perpendicular to the first edge is less than a width of the straight portion.

Abstract: A dynamic calibration method for heterogeneous sensors includes: sensing dynamic objects by a first sensor to generate first sensing data; sensing the dynamic objects by a second sensor to generate second sensing data; performing feature matching between the first sensing data and the second sensing data to determine first valid data and second valid data, and identifying a tracked object from the dynamic objects based on the first valid data and the second valid data; performing feature comparison between the first valid data and the second valid data corresponding to the tracked object to calculate data errors between the first sensor and the second sensor; and calculating a calibration parameter based on the first valid data and the second valid data when the number of the data errors exceeds an error threshold, and adjusting the first sensing data and the second sensing data based on the calibration parameter.

Abstract: A device including at least one processor, and an analog-to-digital (ADC) circuit, wherein the at least one processor is configured to generate an excitation signal and provide the excitation signal to a crystal in a pierce oscillation configuration, wherein after providing the excitation signal, the ADC circuit is configured to obtain as input a signal output from the crystal and convert the signal to a digital output; the at least one processor is configured to compare the digital output of the ADC circuit to a plurality of thresholds and based on the comparisons is further configured to drive the crystal to cause the crystal to operate as a pierce oscillator and to generate a clock signal from at least of one of the comparisons.

Abstract: This application provides an exception locating method includes: A first device receives a first exception signal which changes abruptly from a first communication signal when the first communication signal passes through a location of an exception on a first line. The first device receives exception alarm information which is sent by the second device after the second device receives a second exception signal, the second exception signal is a signal that changes abruptly from a second communication signal when the second communication signal passes through the location of the exception. The first device determines the location of the exception based on a first time interval, where the first time interval is an interval between time at which the first exception signal is received and time at which the exception alarm information is received.

Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.

Abstract: A two-stage machine learning model is used to for categorization of a dataset, such as transactions. A plurality of complementary base machine learning models are used to generate initial inference results and associated measures of inference confidence from the dataset, which are collected as a meta dataset. Each of the complementary models is associated with a different part of the dataset in which it has a higher accuracy in that part than the other models. The meta dataset is provided as input to a meta machine learning model, which is trained to produce a final inference result, and a confidence score model, which is trained to produce a confidence score associated with the final inference result.

Abstract: A super resolution (SR) image generation circuit includes an image scale-up circuit, a stable SR processing circuit, a generative adversarial network (GAN) processing circuit, and a configurable basic block pool circuit. The image scale-up circuit is arranged to receive and process an input image to generate a scaled-up image. The stable SR processing circuit is arranged to receive a feature map of the input image to generate a stable delta value. The GAN processing circuit is arranged to receive the feature map to generate a GAN delta value. The configurable basic block pool circuit is arranged to dynamically configure a plurality of basic blocks according to a depth requirement of the input image, to generate a configuration result. The SR image generation circuit generates an SR image according to the scaled-up image, the stable delta value, and the GAN delta value.

Abstract: An optical system is provided. The optical system is used for disposing on an electronic device. The optical system includes a movable portion, a fixed portion, a first driving assembly, and a support module. The movable portion is used for connecting to an optical module. The fixed portion is affixed on the electronic device, and the movable portion is movable relative to the fixed portion. The first driving assembly is used for driving the movable portion to move relative to the fixed portion. The movable portion is movably connected to the fixed portion through the support module.

Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.

Abstract: A via structure, a semiconductor structure, and methods for forming the via structure and the semiconductor structure are presented. A via structure includes a first conductive portion through an interconnect structure, a second conductive portion through a substrate and in contact with the first conductive portion, and a liner layer. The liner layer is between the first conductive portion and the interconnect structure, and between the second conductive portion and the substrate. The liner layer includes a portion extending parallel to a surface of the substrate.

Abstract: Some implementations described herein include systems and techniques for fabricating a multi-dimension through silicon via structure in a three-dimensional integrated circuit device. The multi-dimension through silicon via structure includes a first columnar structure having a first width and a second columnar structure including a second width that is greater relative to the first width. The first columnar structure may include a low electrical capacitance and be configured for electrical signaling within the three-dimensional integrated circuit device. The second columnar structure may be configured to provide power to integrated circuitry of the three-dimensional integrated circuit device and also be configured to conduct heat through the three-dimensional integrated circuit device for thermal management of the three-dimensional integrated circuit device. Additionally, a pattern including the second columnar structure may be used for alignment purposes.

Abstract: A medical endoscope image recognition method is provided. In the method, endoscope images are received from a medical endoscope. The endoscope images are filtered with a neural network, to obtain target endoscope images. Organ information corresponding to the target endoscope images is recognized via the neural network. An imaging type of the target endoscope images is identified according to the corresponding organ information with a classification network. A lesion region in the target endoscope images is localized according to an organ part indicated by the organ information. A lesion category of the lesion region in an image capture mode of the medical endoscope corresponding to the imaging type is identified.

Abstract: A “dry” packaging in which a prosthetic heart valve is packaged within a container with hydrogel that can be provided in many forms. Certain embodiments include hydrogel that is preloaded with glycerol or the like. The hydrogel regulates the humidity within the container through a diffusion-driven mechanism if a gradient of humidity between the inside and the outside of the hydrogel exists. Humidity regulation is important to prevent the tissue of the valve structure from drying out. When the partially-hydrated hydrogel is present within container, which is saturated with air of a predefined humidity, the water molecules from the air will be absorbed by the hydrogel if the air humidity is high (i.e. when the thermodynamics favor hydrogel hydration) or vice versa. Various embodiments are configured to also house at least a portion of a delivery device for delivering the prosthetic heart valve.

Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.

Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.

Abstract: A manufacturing method of a semiconductor super-junction device includes the following steps: An n-type substrate is etched in a self-aligning manner using a first insulating layer and a second insulating layer as a mask to form a second groove in the n-type substrate. A gate structure is formed in the second groove.

Abstract: Provided are a circuit control method, a battery controller, a battery management system, a battery, an electrical apparatus, and a vehicle. The circuit control method includes: acquiring an apparatus wake-up signal; determining whether a power source terminal voltage of a charging circuit of a battery on the apparatus is greater than a first threshold and whether a change rate in a first time length is less than a second threshold, wherein the charging circuit is a circuit connecting the battery on the apparatus and a generator, and the power source terminal voltage is an output voltage of the generator; and issuing a first instruction when the power source terminal voltage of the charging circuit of the battery on the apparatus is greater than the first threshold and the change rate in the first time length is less than the second threshold, so that the charging circuit is turned on.

Abstract: An electronic device may display image content via an electronic display by controlling light emission from display pixels of the electronic display. A processor of the electronic device may receive image data destined for a defective display pixel (e.g., dim pixel, dead pixel). The processor may convert a gray level of the image data into a luminance domain to generate a target luminance that would have been emitted by the defective display pixel had the display pixel not been defective. After selecting a compensation mask, the processor may distribute the target luminance of the defective display pixels to nearby non-defective pixels of the electronic display to conceal the presence of the defective display pixel.

Abstract: The present invention relates to a chip tray positioning device, which mainly comprises a frame body, a tray conveying module, a pulling module, a pushing module and a controller. The tray conveying module is disposed on the frame body, electrically connected to the controller and controlled to convey a chip tray from the start area to the end area. The pulling module and the pushing module are disposed on the frame body, electrically connected to the controller and controlled to cause the chip tray to be abutted against the end wall and the lateral wall of the frame body, thereby realizing the positioning of the chip tray and eliminating an error formed in the transfer process of the chip tray. In addition, the controller also controls the pushing module to knock the chip tray at a specific frequency so that the chip tray is vibrated.

Abstract: The present disclosure provides an array substrate, an electronic device and a manufacturing method of the array substrate. The array substrate includes a base substrate, and a first transistor and a second transistor on the base substrate, a first electrode of the first transistor being connected to a second electrode of the second transistor; the array substrate further includes a photodiode including a first electrode, a second electrode, and a photosensitive layer between the first electrode and the second electrode, and the first electrode is electrically connected to a gate of the first transistor. In the arrangement, the first transistor and the second transistor are connected in series to form one control unit, and the uniformity and stability of the control unit are greatly improved.