Abstract: The present disclosure provides a semiconductor device that includes channel layers vertically stacked over a substrate, a gate structure engaging the channel layers, a source/drain (S/D) formation assistance region partially embedded in the substrate and under a bottommost one of the channel layers, and an S/D epitaxial feature interfacing both the S/D formation assistance region and lateral ends of the channel layers. The S/D formation assistance region includes a semiconductor seed layer embedded in an isolation layer. The isolation layer separates the semiconductor seed layer from physically contacting the substrate.

Abstract: Methods for managing a connection pool for cloud-based applications accessing databases are provided. Aspects include establishing a plurality of connections to one or more databases, receiving connection requests from a plurality of cloud-based applications to access the one or more databases, and allocating the connection requests to among the plurality of connections, where the allocation is determined based at least in part on one or more connection pool parameters. Aspects also include monitoring a usage of the plurality of connections by the plurality of applications and updating the one or more connection pool parameters based on an analysis of the usage of the plurality of connections by the plurality of applications.

Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

Abstract: A calibration system includes a head mounted device including an eye tracking (ET) system, processing logic coupled to the ET camera, and a calibration apparatus removably coupled to the head mounted device. The ET camera may take an image of a plurality of 3D objects on the calibration apparatus to collect calibration information and use the calibration information to update eye tracking parameters for the ET camera. The calibration apparatus may include a plurality of 3D pillars or cylinders having varying heights and which are located at varying distances from each other.

Abstract: A circuit includes a power management circuit configured to receive a first or second control signal, and to supply a first, second or third supply voltage. The power management circuit includes a first level shifter circuit, a first header circuit and a latch circuit. The first level shifter circuit is configured to generate a fourth control signal in response to a fifth control signal. The fourth control signal is a level shifted version of the fifth control signal. The first header circuit is configured to supply a first supply voltage of a first voltage supply to a first node in response to the first control signal, or a second supply voltage of a second voltage supply to a second node in response to a first level shifted signal. The latch circuit is configured to generate a first output control signal in response to the first and the fourth control signal.

Abstract: An image processing method includes following operations: generating, by a processor, a sliding window for a target pixel in a plurality of pixels in image data; generating, by the processor, an original brightness histogram of the sliding window according to an original bit depth; generating, by the processor, a low-bit-depth brightness histogram of the sliding window according to a low bit depth; determining, by the processor, a target low-bit-depth range from the low-bit-depth brightness histogram according to the target pixel; extracting, by the processor, a partial original brightness histogram from the original brightness histogram according to the target low-bit-depth range; and performing, by the processor, a histogram equalization process on the partial original brightness histogram according to the original bit depth to generate a final brightness value of the target pixel.

Abstract: A method for system profiling and controlling and a computer system performing the same are provided. In the method, an operating system is operated after the computer system is booted, in which a profiling-controlling system is operated. When the operating system loads and executes a system profiling-controlling program, the profiling-controlling system that simultaneously operates a profiling routine and a controlling routine is initiated. The profiling routine is used to retrieve system kernel data that is generated during operation of the operating system and analyze the system kernel data through a kernel tracing tool. When it is determined that controlling is required, the profiling routine notifies the controlling routine. The controlling routine controls operating parameters of the operating system in real time according to an analysis result generated by the profiling routine.

Abstract: A call registration system includes, for example, a gate (3), a security controller (4), a server (6), and a storage device (5). The security controller (4) includes, for example, a retaining unit (42), a determining unit (41), and a requesting unit (43). When the determining unit (41) determines that information concerning a selected permission floor is not retained by the retaining unit (42), the requesting unit (43) requests a group controller (1) to perform call registration for a normal use floor. When the determining unit (41) determines that the information concerning the selected permission floor is retained by the retaining unit (42), the requesting unit (43) requests the group controller (1) to perform call registration for the selected permission floor.

Abstract: A memory circuit includes a control circuit configured to receive a clock signal including a clock cycle and output control signals based on the clock signal, an input circuit arrangement configured to, responsive to the control signals, pass a latched address to an output of the input circuit arrangement, the latched address including, during a first half of the clock cycle, a read address received at a first input port, and, during a second half of the clock cycle, a write address received at a second input port, an array of single-port memory cells, the memory circuit being configured to perform read and write operations during the respective first and second halves of the clock cycle, and a decoding circuit arrangement configured to, based on the latched address at the output, activate a row of memory cells of the array during each of the first and second clock cycle halves.

Abstract: The present application provides a main catalyst for preparing poly(4-methyl-1-pentene) and a use of the main catalyst. The main catalyst for preparing poly(4-methyl-1-pentene) of the present application has a structure represented by Formula I, in which R1 is selected from hydrogen or phenyl, and when R1 is selected from phenyl, R1 is fused with a naphthalene ring in the Formula I to form an anthracene ring; and R2 is selected from methyl or isopropyl. When the main catalyst of the present application is used in a catalytic system to catalyze homopolymerization of 4-methyl-1-pentene, the catalyst exhibits high catalytic activity, and the prepared poly(4-methyl-1-pentene) has high molecular weight, narrow molecular weight distribution and high isotacticity, and thus has broad market application prospects.

Abstract: A method of identifying a whiteboard based on image tokens includes setting a plurality of image tokens on the whiteboard, obtaining an image including the whiteboard from a camera, employing hardware or software techniques to detect image shaking in order to prevent a display of non-relevant content or privacy-sensitive information, detecting image tokens of the whiteboard by using a machine learning model, applying token tracking to the image tokens to enhance stability and robustness of token detection, calculating coordinates of the image tokens, determining an optimal mapping matrix based on the coordinates of the image tokens, mapping the image based on the optimal mapping matrix to generate a mapped image of the whiteboard, and displaying the mapped image on a screen.

Abstract: A method includes forming first and second gate stacks extending across a semiconductor fin on a substrate; forming source/drain regions in the semiconductor fin, wherein one of the source/drain region is between the first and second gate stacks; forming a dielectric layer laterally surrounding the first and second gate stacks; doping a portion of the dielectric layer between the first and second gate stacks with a dopant; removing the second gate stack to form a gate trench next to the doped first portion of the dielectric layer; performing an annealing process to expand the doped first portion of the dielectric layer toward the gate trench; forming an isolation structure in the gate trench and next to the expanded first portion of the dielectric layer; forming a source/drain contact extending through the dielectric layer to the one of the source/drain regions.

Abstract: A smart display device displaying an appearance of a transportation vehicle comprises a display element, a user interface, and a smart display device. The display element is located in multiple regions along a contour of a vehicle body. The user interface includes a status display region and a function display region, a user defines electronic display contents in the function display region according to preferences, and previews the electronic display contents in the status display region. The electronic display contents include a background and text and/or patterns displayed on the background. The smart display device determines the electronic display contents according to the operation of the user interface to display the electronic display contents on the display element in real-time. The invention also provides a setting method, a method of use, and a non-transitory computer-readable recording medium thereof.

Abstract: A display panel and a method of manufacturing a display panel are provided. The display panel includes: a substrate; a first transistor disposed on the substrate, the first transistor including a first source and a first drain; and a second transistor disposed on the substrate, the second transistor including a second source and a second drain. The first source and the first drain have two metal sub-layers respectively, and the second source and the second drain have three metal sub-layers respectively. Since the first transistor and the second transistor are both included in the display panel, the advantages of the first transistor and the second transistor are respectively utilized, thereby ensuring that the requirements of different thin film transistors for each circuit unit in the display panel are met.

Abstract: A synchronization method includes obtaining a first timestamp difference of a packet on a target link. The first timestamp difference is a difference between a sending timestamp and a receiving timestamp of the packet at a first moment. The synchronization method further includes performing packet selection based on the first timestamp difference to obtain a second timestamp difference; obtaining a delay prediction value of the target link at the first moment, compensating for the second timestamp difference based on the delay prediction value to obtain a compensated timestamp difference; and performing time and/or clock synchronization based on the compensated timestamp difference. The second timestamp difference is compensated for based on the delay prediction value, that is, PDV noise introduced to the target link is compensated for. In this way, the PDV noise is reduced.

Abstract: A clock control circuit module, a memory storage device, and a clock control method are disclosed. The clock control circuit module is configured to: generate a clock signal; receive a first signal and the clock signal and sample the first signal according to the clock signal to generate a first sampling signal and a second sampling signal; obtain first position information corresponding to a first transition point of a first target signal and second position information corresponding to a second transition point of a second target signal according to the first sampling signal and the second sampling signal respectively; and evaluate a frequency shift status between the first signal and the clock signal according to the first position information and the second position information.

Abstract: A luminance compensation circuit includes: a light-emitting circuit; a luminance detector electrically connected to a first power terminal, a second power terminal, and a first node; a reading device electrically connected to the first node; and a timing controller electrically connected to the reading device and the light-emitting circuit.

Abstract: An array substrate and a display panel are disclosed. The display panel includes the array substrate. An ion injection stopper layer and an active layer of the array substrate correspond to at least part of the channel part. The ion injection stopper layer blocks ions from being injected into the channel part. Therefore, an effective channel length of oxide TFTs is reduced. A width of a channel of the oxide TFTs can be reduced without changing a width-length ratio of the oxide TFTs. As such, a size of the oxide TFTs can be reduced, and an aperture ratio of the display panel is increased.

Abstract: A memory device is provided, including an array of bit cells and a set of tracking cells. The set of tracking cells is arranged adjacent to the array of bit cells along a first direction. The set of tracking cells includes a set of first tracking cells configured to perform a read tracking operation and a set of second tracking cells configured to perform a write tracking operation and arranged adjacent to the set of first tracking cells along a second direction. First tracking cells in the set of first tracking cells are coupled in series with each other and arranged along the second direction, and second tracking cells in the set of second tracking cells are coupled in series with each other and arranged along the second direction.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes first nanostructures formed over a substrate along a first direction, and second nanostructures formed over the substrate along the first direction. The semiconductor structure includes a first gate structure formed over the first nanostructures along a second direction, and a second gate structure formed over the second nanostructures along the second direction. The semiconductor structure also includes a dielectric wall structure between the first gate structure and the second gate structure along the second direction. The dielectric wall structure includes a top portion and a bottom portion, and a top width of a top surface of the top portion is smaller than a bottom width of a bottom surface of the bottom portion of the dielectric wall structure.