Abstract: A structured light scanning method includes a light projector projecting a group of structured light to an object, an image capturing device capturing a group of images generated by the object reflecting the group of structured light, an image processor obtaining a pixel luminosity distribution of an image in the group of images, the image processor determining a reflection state of the image from the pixel luminosity distribution, the image processor determining whether to include the image in generating a depth map according to the reflection state, and the image processor decoding at least one image from the group of images to generate the depth map.

Abstract: Provided is a pixel driving circuit. The pixel driving circuit includes a reset unit, a storage unit, an initialization unit, a drive unit, a threshold compensation unit, and a data write unit. A first terminal of the reset unit is configured to input the signal output by a reset power supply. A second terminal of the reset unit is connected to the control terminal of the drive unit and configured to provide the reset power supply for the control terminal of the drive unit during a power-on period. During the power-on period of the pixel driving circuit, the reset unit provides the reset power supply for the drive unit and performs reset control on the drive unit, so that the drive unit is prevented from being abnormally turned on during a power-on stage, thereby avoiding a screen flicker phenomenon.

Abstract: A structure and a method of forming are provided. A first work function layer is formed over a first fin and terminates closer to the first fin than an adjacent second fin. A second work function layer is formed over the first work function layer and terminates closer to the second fin than the adjacent second fin. A third work function layer is formed over the first work function layer and the second fin. A conductive layer is formed over the third work function layer.

Abstract: Provided is a voice recognition method and a voice recognition apparatus, and an air conditioner. The method includes: acquiring first voice data; adjusting, according to the first voice data, a collection state of second voice data to obtain an adjusted collection state, and acquiring the second voice data based on the adjusted collection state; and performing far-field voice recognition on the second voice data using a preset far-field voice recognition model so as to obtain semantic information corresponding to the acquired second voice data. The application can solve the problem in which far-field voice recognition performance is poor when a deep learning method or a microphone array method is used to remove reverberation and noise from far-field voice data, thereby enhancing far-field voice recognition performance.

Abstract: A wheeled vehicle includes a vehicle body, a vibration absorbing element, an auxiliary arm, a wheel, and a driving member. The vehicle body includes a fixing plate. The housing connected to the fixing plate. The vibration absorbing element includes a first end and a second end. The first end is fixed to the housing. The auxiliary arm includes a connecting end and a free end. The connecting end is connected to the housing. The free end is configured to swing relative to the connecting end. The free end is fixed to the second end. The wheel includes an axle, and the axle is rotationally connected to the free end. The driving member is fixed to the housing and configured to drive the wheel.

Abstract: An electronic device includes a temporary memory, a non-volatile memory and a processor. The temporary memory includes at least one secure region. The non-volatile memory is configured to store at least one higher-level secure program and a plurality of commands. The processor is connected to the temporary memory and the non-volatile memory for executing the plurality of commands to: when receiving a wake-up command, initialize the at least one secure region; and through the at least one higher-level secure program, recover the at least one secure region, or decrypt encrypted data stored in the non-volatile memory to recover the at least one secure region. In addition, a hibernation recovery method is also disclosed herein.

Abstract: The present invention provides a text classification backdoor attack method, system, device and a computer storage medium. The method includes: training a pretraining model by using a clean training set to obtain a clean model; generating a pseudo label data set by using a positioning label generator; performing multi-task training on a Sequence-to-Sequence model by using the pseudo label data set to obtain a locator model; generating a backdoor data set by using the locator model; and training the clean model by using the backdoor data set to obtain a dirty model. A pseudo label data set is generated by using a pretrained clean model without manual annotation. A backdoor attack location in a text sequence may be dynamically predicted by using a locator model based on a Sequence-to-Sequence and multi-task learning architecture without manual intervention, and a performance indicator obtained by dynamically selecting an attack location is better.

Abstract: An apparatus for buffing a shoe part includes a housing adapted to be articulated around at least a portion of the footwear part. A rotating spindle is positioned in the housing and has a buffing surface for engagement with the footwear part. A carriage is slideably connected to the housing and holds the spindle such that the buffing surface can be moved closer to and further away from the footwear part. An actuator is in the housing and in contact with the carriage. The actuator applies force to the carriage to increase the force of the buffing surface onto the footwear part. A biasing member is in the housing and in contact with the carriage. The biasing member exerts force onto the carriage in a direction opposite the force exerted by the actuator.

Abstract: An electronic device including a metal housing, a first antenna module, and a second antenna module is disclosed. The metal housing includes a back cover and a frame, the frame is located on a side of the back cover, and a slot is arranged between the back cover and the frame. The frame includes two slits and a segment, and the two slits are connected with the slot to form a U shape. The segment is surrounded by the two slits and the slot. The first antenna module includes an antenna radiator formed by the segment. The antenna radiator is coupled to the back cover across the slot through multiple connecting portions. The second antenna module is disposed on the connecting portions to be coupled to the back cover and grounded, and an antenna coupling gap exists between the second antenna module and the frame.

Abstract: A pixel array may include a group of time-of-flight (ToF) sensors. The pixel array may include an image sensor comprising a group of pixel sensors. The image sensor may be arranged among the group of ToF sensors such that the image sensor is adjacent to each ToF sensor in the group of ToF sensors.

Abstract: A system for storing wafer is provided. The system includes a wafer box, an installing member, a detection tube, a control unit, and a detection unit. The wafer box includes an outlet connector and an inlet connector extending a wall of the wafer box. The installing member covers the wafer box to form a sealed receiving room. Two ends of the detection tube are coupled to the outlet connector and the inlet connector. The control unit are configured to output a first control signal to the detection unit. The detection unit includes a first sensor arranged in the detection tube. The first sensor is configured to detect a property of gas to obtain data of an environment where the wafer is stored upon the first control signal. A related system for monitoring pollution of wafer is also provided.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure over a substrate. A metal layer overlies the gate dielectric structure. A conductive layer overlies the metal layer. A polysilicon layer contacts opposing sides of the conductive layer. A bottom surface of the polysilicon layer is aligned with a bottom surface of the conductive layer. A dielectric layer overlies the polysilicon layer. The dielectric layer continuously extends from sidewalls of the polysilicon layer to an upper surface of the conductive layer.

Abstract: Devices and methods of manufacture for a graduated, “step-like,” semiconductor structure having two or more resonator trenches. A semiconductor structure may comprise a first resonator and a second resonator. The first resonator comprising a first metallic resonance layer and a capping plate having a bottom surface that is a first distance from a distal end of the first metallic resonance layer 128. The second resonator comprising a second metallic resonance layer and the capping plate, in which the bottom surface is a second distance from a from a distal end of the second metallic resonance layer 128b, and in which first distance is different from the second distance.

Abstract: A package structure includes a first dielectric layer disposed on a first patterned circuit layer, a first conductive via in the first dielectric layer and electrically connected to the first patterned circuit layer, a circuit layer on the first dielectric layer, a second dielectric layer on the first dielectric layer and covering the circuit layer, a second patterned circuit layer on the second dielectric layer and including conductive features, a chip on the conductive features, and a molding layer disposed on the second dielectric layer and encapsulating the chip. The circuit layer includes a plurality of portions separated from each other and including a first portion and a second portion. The number of pads corresponding to the first portion is different from that of pads corresponding to the second portion. An orthographic projection of each portion overlaps orthographic projections of at least two of the conductive features.

Abstract: A method of generating an IC layout diagram includes overlapping a channel region of an upper transistor of a complementary field-effect transistor (CFET) in an IC layout with a gate region of the CFET, thereby defining a channel overlap region, positioning an isolation region in the IC layout, the isolation region including an entirety of the channel overlap region, intersecting the isolation region with a conductive region, and generating an IC layout diagram based on the IC layout.

Abstract: A method includes: turning on a first switch coupled between a first array of memory and a voltage supply according to a first charge signal; turning on a second switch coupled between a second array of memory and the voltage supply according to a second charge signal different from the first charge signal; and generating the first charge signal and the second charge signal according to a word line address. The second array of memory is located between the second switch and the first array of memory.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.

Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. In response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.

Abstract: A winding device includes a pair of outer pins oppositely arranged in a first direction with a periphery for an electrode assembly to wind around, adjusting members configured to reciprocate in a second direction perpendicular to the first direction to drive the pair of outer pins to move away from or close to each other to increase or reduce a distance between the pair of outer pins, a pair of inner pins arranged oppositely in the first direction between the pair of outer pins and configured to move independent of the adjusting members to clamp or release the electrode assembly, and an elastic returning member configured to apply an elastic force in the first direction to at least one of the pair of inner pins such that the pair of inner pins have a tendency to be close to each other.