Patents by Inventor Wei Yu

Wei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250119825
    Abstract: Apparatus, methods, and computer-readable media for facilitating determining or predicting a communication state of a UE based on, for example, measurements performed at the UE are disclosed herein. The communication state of the UE, such as an HST state or a non-HST state, may also be associated with a mobility state, such as stationary or moving. The UE may communicate based on the communication state. An example method for wireless communication at a UE includes establishing a connection with a network node. The example method also includes measuring one or more signals received from the network node over a time period. The example method also includes communicating with the network node based on a communication state of the UE, the communication state of the UE based at least in part on a history of measurements performed on the one or more signals received over the time period.
    Type: Application
    Filed: March 29, 2022
    Publication date: April 10, 2025
    Inventors: Jie MAO, Hong YU, Wei LI, Nanrun WU, Jie ZHU, Xinyu WANG, Tom CHIN
  • Publication number: 20250120166
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Hou-Yu Chen, Ching-Wei Tsai, Chih-Hao Wang, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu
  • Publication number: 20250115075
    Abstract: Provided is a rim spoke, including a spoke rope and nipples. Mounting heads are fixedly sleeved on both ends of the spoke rope; through mounting holes are formed in the nipples; the nipples are fixedly sleeved on the mounting heads by means of the mounting holes; and the spoke rope is made of a textile fiber material. When the textile fiber spoke rope in a high tension state is subjected to a heavy impact, part of an impact force is cushioned due to the flexibility and strength margin of the spoke rope itself, so that the original characteristics of the spoke rope can still be kept under an extreme impact force without irreversible deformation, thereby reducing riding failure rate of riding, ensuring the riding safety, reducing the daily maintenance requirement of a wheel, and reducing costs.
    Type: Application
    Filed: February 9, 2022
    Publication date: April 10, 2025
    Applicant: XIAMEN HONGJIWEIYE INDUSTRIAL CO., LTD.
    Inventors: Shunhe CHEN, Fugui YU, Wei MENG, Na ZHANG
  • Publication number: 20250118716
    Abstract: A semiconductor package includes a semiconductor element, at least one electronic die, at least one optical die, an encapsulant, and a substrate. The semiconductor element has a first side and a second side opposing to the first side. The at least one electronic die is disposed over the first side. The at least one optical die is disposed over the first side and next to the at least one electronic die. The encapsulant is disposed on the first side and covers the at least one electronic die, where a sidewall of the at least one optical die is distant from the encapsulant, and a sidewall of the encapsulant is aligned with a sidewall of the semiconductor element. The substrate is disposed over the second side, where the at least one electronic die is electrically coupled to the substrate and the at least one optical die through the semiconductor element.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Cheng-Shiuan Wong, Chia-Shen Cheng, Hsuan-Ting Kuo, Hao-Jan Pei, Hsiu-Jen Lin
  • Publication number: 20250116937
    Abstract: A lithography method includes the steps which are mentioned below. A photoresist layer is formed over a substrate. The photoresist layer is exposed. The photoresist layer is developed. A vacuum treatment is performed to the photoresist layer. The substrate is etched by using the photoresist layer as an etch mask.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 10, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hui WENG, Wei-Han LAI, Hsien-Chung HUANG, Ching-Yu CHANG
  • Publication number: 20250120123
    Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent the gate dielectric layer, wherein the first gate spacer comprises an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface towards the outer surface of the first gate spacer.
    Type: Application
    Filed: January 24, 2024
    Publication date: April 10, 2025
    Inventors: Chun-Fu LU, Lung-Kun CHU, Jia-Ni YU, Chung-Wei HSU, Shih-Hao LAI, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250116931
    Abstract: A photoresist composition includes a solvent and a polymer. The polymer comprises a polymer backbone, an acid labile group monomer, a photo acid generator monomer and a quencher monomer. The acid labile group monomer is bonded to the polymer backbone. The acid labile group monomer is acid cleavable. The photo acid generator monomer is bonded to the polymer backbone. The quencher monomer is bonded to the polymer backbone.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hui Weng, Wei-Han Lai, Ching-Yu Chang
  • Publication number: 20250116932
    Abstract: A method for manufacturing a semiconductor device includes forming a photoresist layer from a photoresist composition over a substrate. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a patterned photoresist. The photoresist composition includes a photoactive compound, a thiol-containing polymer comprising an aryl group and an acid labile group. The thiol group can crosslink the polymer via oxidative disulfide formation and/or thiol-ene/yne “click” reaction.
    Type: Application
    Filed: March 11, 2024
    Publication date: April 10, 2025
    Inventors: Li-Po YANG, Wei-Han LAI, Kuan-Hsin LO, Ching-Yu CHANG
  • Publication number: 20250117360
    Abstract: A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.
    Type: Application
    Filed: October 30, 2024
    Publication date: April 10, 2025
    Applicant: Intel Corporation
    Inventors: Jorge Parra, Wei-yu Chen, Kaiyu Chen, Varghese George, Junjie Gu, Chandra Gurram, Guei-Yuan Lueh, Stephen Junkins, Subramaniam Maiyuran, Supratim Pal
  • Publication number: 20250115783
    Abstract: Disclosed herein is a 2K clearcoat coating composition including (A) from 10% to 70% by weight of a first resin having at least one primary hydroxyl group; (B) from 2% to 40% by weight of a second resin including a resin (B-1) having at least one primary hydroxyl group and/or a resin (B-2) having at least one secondary hydroxyl group; and (C) a crosslinker including at least one polyisocyanate and at least one amino resin, and the weight percentages of components (A) and (B) are based on the total weight of the coating composition and the ratio by weight between components (A) and (B) is in a range of from 6:1 to 1:2. Further disclosed herein is an article coated by the coating composition and the article may have metal substrates.
    Type: Application
    Filed: June 14, 2023
    Publication date: April 10, 2025
    Inventors: Yang ZHANG, Wei ZHANG, Lei HE, Jing Yu HUANG, Xiao Gang YOU
  • Publication number: 20250116847
    Abstract: An optical photographing lens assembly includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof. The second lens element has refractive power. The third lens element has refractive power. The fourth lens element has refractive power. The fifth lens element with refractive power has an image-side surface being convex in a paraxial region thereof, wherein an object-side surface and the image-side surface of the fifth lens element are both aspheric. The sixth lens element with refractive power has an object-side surface and an image-side surface being both aspheric. The optical photographing lens assembly has a total of six lens elements with refractive power.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 10, 2025
    Inventor: Wei-Yu CHEN
  • Patent number: 12270709
    Abstract: An infrared sensor uses an infrared lens with infrared filtering and focusing functions. Thus, an infrared filter can be omitted to reduce the costs and volume. In addition, a getter on the inside of a metal cover of the infrared sensor can be activated when the metal cover is soldered to the substrate of the infrared sensor. Therefore, the packaging process of the infrared sensor can be simplified.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: April 8, 2025
    Assignee: TXC CORPORATION
    Inventors: Tzong-Sheng Lee, Jen-Wei Luo, Chia-Hao Weng, Chun-Chi Lin, Ting-Chun Hsu, Hui-Jou Yu, Yi-Hung Lin, Sung-Hung Lin
  • Patent number: 12272992
    Abstract: A stator structure is provided and includes a plurality of first lamination layers, a plurality of second lamination layers, two third lamination layers and two oil spraying rings. The second lamination layers are sandwiched in between the first lamination layers. The second lamination layer located in the middle of the stator structure is sandwiched in between the two third lamination layers. The two oil spraying rings are connected to two first lamination layers located at outermost sides. Another stator structure is provided and includes a plurality of first lamination layers, a second lamination layer and two oil spraying rings. The second lamination layer is sandwiched in between two first lamination layers. The two oil spraying rings are connected to two first lamination layers located at outermost sides. By means of the arrangement of the aforesaid stator structure, the invention can effectively improve heat dissipating effect for oil cooling.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 8, 2025
    Assignee: XPT (NANJING) E-POWERTRAIN TECHNOLOGY CO., LTD.
    Inventors: Zhengyu Tang, Di Wang, Zhixin Yu, Wei Wang, Jiebao Li, Li Han
  • Patent number: 12272082
    Abstract: The disclosed method includes acquiring sample models and marking sample feature points; selecting target feature points and regional points on bones; transforming the target feature points and the regional points, and registering the target feature points with the sample feature points; formulating a strategy for assigning impact factors to the sample models, linearly combining all sample models to construct an initial model, and determining initial feature points corresponding to the target feature points in the initial model; adjusting the strategy according to the distance between initial feature points and the target feature points, selecting the strategy corresponding to the minimum distance as an optimal strategy, and determining an optimal initial model; determining a matching point corresponding to each regional point in the optimal initial model, and calculating a transformation relationship; and transmitting all points of the optimal initial model according to the transformation relationship to obt
    Type: Grant
    Filed: March 13, 2024
    Date of Patent: April 8, 2025
    Assignees: Vostro Medical Technology (Tianjin) Co., Ltd, The Fourth Medical Center of PLA General Hospital
    Inventors: Mingjun Fu, Wei Chai, Yuan Zhang, Mingmin Ren, Guoqing Yu, Linshuai He, Mingcheng Shen, Zhongwei Wang, Chengcheng Shang
  • Patent number: 12273108
    Abstract: The invention introduces an apparatus and a method for expanding round keys during data encryption. The method includes: configuring a word-processing circuitry to operate in a first mode to calculate a first intermediate calculation result corresponding to an even-number round key according to a last double word of a 0th double word to a 7th double word in each even-number clock cycle starting from a 2nd clock cycle; and configuring the word-processing circuitry to operate in a second mode to calculate a second intermediate calculation result corresponding to an odd-number round key according to the last double word of the 0th double word to the 7th double word in each odd-number clock cycle starting from a 3rd clock cycle. In the first mode, a first data path is formed in the word-processing circuitry, which includes a word split circuitry, a rotate-word circuitry, a substitute-word circuitry, a round-constant circuitry and a word concatenation circuitry.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: April 8, 2025
    Assignee: SILICON MOTION, INC.
    Inventors: Wun-Jhe Wu, Po-Hung Chen, Chiao-Wen Cheng, Jiun-Hung Yu, Chih-Wei Liu
  • Patent number: 12271006
    Abstract: Disclosed is a cost-effective method to fabricate a multifunctional collimator structure for contact image sensors to filter ambient infrared light to reduce noises. In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; a plurality of via holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, and wherein the conductive layer is formed over at least one of the following: the first surface of the first dielectric layer and a portion of sidewalls of each of the plurality of via holes, and wherein the conductive layer is configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yu Chen, Yen-Chiang Liu, Jiun-Jie Chiou, Jia-Syuan Li, You-Cheng Jhang, Shin-Hua Chen, Lavanya Sanagavarapu, Han-Zong Pan, Chun-Peng Li, Chia-Chun Hung, Ching-Hsiang Hu, Wei-Ding Wu, Jui-Chun Weng, Ji-Hong Chiang, Hsi-Cheng Hsu
  • Patent number: 12272557
    Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Lun Lin, Chia-Wei Hsu, Xiong-Fei Yu, Chi On Chui, Chih-Yu Hsu, Jian-Hao Chen
  • Patent number: 12272637
    Abstract: Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wen-Shiang Liao, Chih-Hang Tung, Chen-Hua Yu, Chewn-Pu Jou, Feng Wei Kuo
  • Patent number: 12272592
    Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
    Type: Grant
    Filed: May 15, 2024
    Date of Patent: April 8, 2025
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Patent number: 12272886
    Abstract: An antenna device includes a differential-line, a first metal and a second metal. The differential-line includes a first line and a second line. The first metal and second metal are coupled to the first line and second line respectively. The first metal and second metal have different shapes and/or different sizes. The first metal and second metal form symmetric or asymmetric dipole. The first metal and second metal can be disposed on the same plane or different planes, can be electrically insulated and can have a first slot and a second slot respectively. The antenna device can further include a base coupled to the first line and second line. The base can be a daughter board having a front-end module or not. The IC package in daughter board can have different sizes. The daughter board can be offset by different distances and can be coupled to a mother board.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: April 8, 2025
    Assignee: IWAVENOLOGY CO., LTD.
    Inventors: Chong-Yi Liou, Wei-Ting Tsai, Jin-Feng Neo, Zheng-An Peng, Tsu-Yu Lo, Zhi-Yao Hong, Tso-An Shang, Je-Yao Chang, Chien-Bang Chen, Shih-Ping Huang, Shau-Gang Mao