Abstract: A heterogeneous multi-core apparatus includes a plurality of cores. The plurality of cores include at least one high-performance core and at least one energy-efficient core. Maximum power consumption of any one of the at least one high-performance core is greater than maximum power consumption of any one of the at least one energy-efficient core. A maximum computing capacity of any one of the at least one high-performance core is greater than a maximum computing capacity of any one of the at least one energy-efficient core. A first core of the plurality of cores may allocate a first computing resource to a first thread, and allocate a second computing resource to a second thread. The first computing resource and the second computing resource belong to a second core of the plurality of cores.

Abstract: Provided are a transistor, a 3D stacked semiconductor device, a manufacturing method thereof, and an electronic device. The transistor includes a first electrode and a second electrode arranged on a substrate, a semiconductor layer arranged between the first electrode and the second electrode, and a gate electrode insulated from the semiconductor layer; the first electrode and the second electrode are separated in a first direction parallel to the substrate; the gate electrode extends along a second direction parallel to the substrate, the gate electrode includes a sidewall extending along the second direction and two end surfaces, one end surface is configured to be connected with a word line; at least a portion of the sidewall of the gate electrode is surrounded by a semiconductor layer; the first direction intersects with the second direction.

Abstract: Described herein is a capsule (1000) comprising a front cover (1100) having a front wall (1110) having a front wall top edge (1112), a first side wall (1120) having a first side wall extension (1122), a second side wall (1130) having a second side wall extension (1132), and a bottom wall (1140), where both the first and the second side walls extensions (1122, 1132) extend beyond the front wall top edge (1112) relative to the bottom wall(1140), the capsule (1000) further comprises a back cover (1200) coupled to the front cover (1100) having a back wall (1210) and a top wall (1250), where the back wall (1210) includes a recess hinge (1212), where a portion of the back wall (1210) above the position of the hinge (1212) and the top wall (1250) are configured as a back flap (1214), and where the coupled front and back covers (1100, 1200) define a capsule interior.

Abstract: A system for navigating a mobile object receives satellite navigation signals from a plurality of satellites. Using one or more of the satellite navigation signals from the plurality of satellites, for each respective channel of a plurality of channels, the system generates an estimate of clock error of a clock of the mobile object using a first error correction stage and generates an estimate of a respective carrier tracking error for the respective channel using a second error correction stage that is distinct from the first error correction stage. In accordance with the estimate of the clock error and the estimate of the respective carrier tracking error for each of the plurality of channels, the system computes position and velocity estimates for the mobile object. The system performs a navigation function for the mobile object in accordance with the computed position and velocity estimates for the mobile object.

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a controller, a first mold compound surrounding the controller, a plurality of semiconductor dies, a second mold compound surrounding the plurality of semiconductor dies, and one or more through-mold interconnects electrically coupling the controller to the plurality of semiconductor dies.

Abstract: A collapsible supplemental illumination device for a sighting device, including an illumination unit, a damping motion unit, a locking mechanism, and a position detection device. The damping motion unit is fixedly mounted on a main body of the sighting device. The damping motion unit is connected to the locking mechanism. The position detection device is provided on the locking mechanism. The illumination unit is rotatably connected to the damping motion unit through the locking mechanism. A control method of the collapsible supplemental illumination device is further provided.

Abstract: The present disclosure is directed to methods of using salivary exosomes to detect and treat Sjögren's syndrome in a subject.

Abstract: Methods and apparatus for a radar system having an array including a series of concentric rings of array elements, wherein the concentric rings that have a shape defined by respective ellipses that increase in size from a center that is common to the respective ellipses. The series of concentric rings can include multiple groups of the concentric rings, wherein the concentric rings in each successive group are larger in size than the concentric rings in the first group.

Abstract: A method comprises: displaying a target image and an effect control on a target interface; determining a target effect mode in response to interaction with the effect control, wherein the target effect mode represents an effect to be added to the target image, wherein the effect comprises a static effect without changing target image position information and a dynamic effect with changing target image position information, and for target static effect and target dynamic effect that have an associated relationship, the target dynamic effect is adjacent to the target static effect in an order of addition, and the target dynamic effect is added after the target static effect; and displaying the image processed with effect on the target interface, wherein the image processed with effect is obtained by adding static effect and dynamic effect corresponding to the target effect mode to the target image.

Abstract: A method is provided for acquiring a signal from a satellite in a global navigation satellite system. The signal includes a pseudorandom code. The method includes, for each time period of a plurality of time periods: generating samples of the signal, segments of the samples of the signal are correlated with a local copy of the pseudorandom code, thereby producing correlation values for the time period. A discrete Fourier transform is performed using, as inputs, the correlation values for the respective time period, thereby producing a frequency representation of the correlation values for the time period. The frequency representations of the correlation values for the plurality of time periods are combined according to a data hypothesis. When a magnitude of the combined frequency representations meets predefined criteria, a frequency corresponding to the magnitude is selected as a tracking frequency for the satellite.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for using memory-optimized contrastive learning to train image encoder and text encoder neural networks.

Abstract: A test system for a vehicle-mounted antenna. In the test system, when a bearing face is connected to a reflecting plate or when the reflecting plate extends from the bearing face, the testing system for a vehicle-mounted antenna can be used for a semi-anechoic chamber test; and when the bearing face is not connected to the reflecting plate or when the reflecting plate is retracted into the bearing face, the test system for a vehicle-mounted antenna can be used for a fully anechoic chamber test. That is to say, the test system for a vehicle-mounted antenna not only has the fully anechoic chamber testing function, but also has the semi-anechoic chamber testing function, and the two functions can be conveniently switched by means of the mounting/removal or extension/retraction of the reflecting plate.

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a controller, a first mold compound surrounding the controller, a plurality of semiconductor dies, a second mold compound surrounding the plurality of semiconductor dies, and one or more through-mold interconnects electrically coupling the controller to the plurality of semiconductor dies.

Abstract: The present disclosure relates to compositions, methods and kits for the isolation of extracellular vesicles. The compositions, methods and kits can comprise a high-density liquid reagent that facilitates the sequestration of extracellular vesicles bound to magnetic beads.

Abstract: A construction method for reconstructing and expanding a ship lock in suit is provided. A flood gate in an upper lock head section of a constructed ship lock is used as a water-retaining cofferdam during a construction period. A remaining part of the constructed ship lock is cut off downstream from a target cutting surface located in a lock chamber section of the constructed ship lock, and a new ship lock is constructed downstream. A bank-side pier structure between the upper lock head section of the constructed ship lock and the new ship lock is cut to a first preset elevation, and two water-retaining and seepage control lines are added, and a cutoff buttress is constructed. An upper navigation wall section of the constructed ship lock and the upper lock head section of the constructed ship lock are reconstructed, and another water-retaining and seepage control line is added.

Abstract: A system of predicting sensitivity of Klebsiella against meropenem includes comprises a computer readable storage medium on which is stored a computer program. An Exp (?k) power value calculation method is implemented when the computer program is executed by a processor. The Exp(?k) power value calculation method comprises-includes following computing steps: S1: k value is calculated according to formula I, k = - 1.44 + 0.708 × ( C ? 1 - 0.252 2.567 ) - 0.66 × ( C ? 2 - 0.981 5.69 ) + 0.088 × ( C ? 3 - 0.952 0.652 ) + 3.048 × ( C ? 4 - 0.469 1.095 ) - 0.46 × ( C ? 5 - 0.296 0.67 ) S2: Exp(?k) power value with natural constant e as base and ?k as exponent is calculated.

Abstract: A semiconductor device includes one or at least two capacitors stacked along a direction perpendicular to a substrate. At least one of the capacitors includes a first plate and a second plate, and a dielectric layer between the first plate and the second plate. The first plate includes a first body structure and at least two first branch layers arranged at intervals along a direction perpendicular to the substrate, the first body structure includes a first conductive layer and a second conductive layer alternately stacked along the direction perpendicular to the substrate, the first plate further includes a groove between adjacent first branch layers, the groove extends along a direction parallel to the substrate, and at least part of the dielectric layer and at least part of the second plate are within the groove. Implementing all of the above improves the capacity of the capacitor.

Abstract: A semiconductor package assembly includes a substrate, a die stack including at least a bottom die, an inert top spacer, and at least a first inert base spacer. The inert top and base spacers are exclusive of any circuits. A top surface of the inert top spacer is directly attached to a bottom surface of the bottom die in the die stack. A top surface of the first inert base spacer is directly attached to a bottom surface of the inert top spacer and a bottom surface of the first inert base spacer is directly attached to the substrate. The footprint of the inert base spacer is smaller than the footprint of the inert top spacer. In some embodiments, the footprint of the inert base spacer is positioned entirely within the footprint of the inert top spacer.

Abstract: A semiconductor device assembly includes a semiconductor die, a substrate, and a spacer directly coupled to the substrate. The spacer includes a flexible main body and a support structure embedded in the flexible main body, wherein the support structure has a higher stiffness than the flexible main body. The spacer carries the semiconductor die. The flexible main body of the spacer mitigates the effects of thermomechanical stress, for example caused by a mismatch between the coefficient of thermal expansion of the semiconductor die and the substrate. The embedded support structure provides strength needed to support the semiconductor die during assembly.