Patents by Inventor Wei Yu

Wei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12144075
    Abstract: A lighting device connects to an external power supply and includes a light emitting load and a secondary load. A temperature measurement is obtained related to a temperature of the external power supply. The secondary load is activated, thereby allowing the secondary load to be powered by the external power supply, when the temperature measurement is below a threshold. Thus, in cold conditions, an increased load is presented to the external power supply to assist start up of the external power supply in cold conditions.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: November 12, 2024
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Wei Li, Yuanqiang Liu, Meiping Mao, Yuan Xin Chen, Ru Yu Li
  • Patent number: 12143022
    Abstract: A control circuit for controlling power switch in switching power supply circuit. The optimization circuit comprises an adaptive amplitude jitter generating circuit, a comparison circuit and a trigger circuit. The adaptive amplitude jitter generating circuit is used to generate a periodic amplitude jitter signal according to the feedback voltage signal indicative of the output of the switching power supply circuit. The comparison circuit is used to compare the sampled voltage signal with periodic amplitude jitter signal, and generate an output signal with periodic fluctuations. The trigger circuit is used for outputting the control signal for driving the power switch according to the output signal with periodic fluctuations and the clock signal.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: November 12, 2024
    Assignee: Shenzhen Kiwi Instruments Corporation
    Inventors: Wei Zhao, Xiufeng Yu, Bo Zhang
  • Patent number: 12142565
    Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
  • Patent number: 12142657
    Abstract: A semiconductor device and related method for forming a gate structure. In some embodiments, a semiconductor device includes a fin extending from a substrate. In some cases, the fin includes a plurality of semiconductor channel layers. In some examples, the semiconductor device further includes a gate dielectric surrounding each of the plurality of semiconductor channel layers. In some embodiments, a first thickness of the gate dielectric disposed on a top surface of a topmost semiconductor channel layer of the plurality of semiconductor channel layers is greater than a second thickness of the gate dielectric disposed on a surface of another semiconductor channel layer disposed beneath the topmost semiconductor channel layer.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Feng Yu, Jiao-Hao Chen, Chih-Yu Hsu, Chih-Wei Lee, Chien-Yuan Chen
  • Patent number: 12144065
    Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Da Cheng, Hsiu-Jen Lin, Cheng-Ting Chen, Wei-Yu Chen, Chien-Wei Lee, Chung-Shi Liu
  • Patent number: 12142682
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chandrashekhar Prakash Savant, Kin Shun Chong, Tien-Wei Yu, Chia-Ming Tsai, Ming-Te Chen
  • Patent number: 12140588
    Abstract: A target cell statistical method, apparatus and system are provided. A cell image of a blood specimen is acquired by a cell image analysis apparatus. The blood specimen is derived from a blood sample to be tested. A number of target cells and a number of reference cells in the cell image are automatically identified by the cell image analysis apparatus. A number of reference cells in the blood sample to be tested is acquired by the cell image analysis apparatus, and a number of target cells in the blood sample to be tested is calculated by the cell image analysis apparatus, based on the number of target cells and the number of reference cells in the cell image and the number of reference cells in the blood sample to be tested.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: November 12, 2024
    Assignee: Shenzhen Mindray Bio-Medical Electronics Co., Ltd.
    Inventors: Bo Ye, Wei Luo, Yuan Xing, Shan Yu, Qiaoni Chen
  • Patent number: 12139554
    Abstract: Compounds for targeting and agents for imaging, prostate-specific membrane antigen (PSMA) are disclosed. Methods of synthesizing compounds and imaging agents, as well as methods for imaging PSMA are also disclosed. The imaging agents disclosed are suitable for PET and SPECT imaging.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: November 12, 2024
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventors: Eric Wang, Hartmuth C. Kolb, Anna Katrin Szardenings, Changhui Liu, Joseph C. Walsh, Gang Chen, Anjana Sinha, Dhanalakshmi Kasi, Chul Yu, Umesh B. Gangadharmath, Wei Zhang, Tieming Zhao, Vani P. Mocharla
  • Publication number: 20240369926
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a photoresist layer over a substrate, exposing the photoresist layer to radiation to form a pattern therein, and selectively removing portions of the photoresist layer that are not exposed to the radiation to form a patterned photoresist layer. The photoresist layer comprises a fluorine-containing polymer including a crosslinking group and a photoactive compound.
    Type: Application
    Filed: May 2, 2023
    Publication date: November 7, 2024
    Inventors: Li-Po YANG, Ching-Yu CHANG, Kuan-Hsin LO, Wei-Han LAI
  • Publication number: 20240369929
    Abstract: A method of manufacturing a semiconductor device includes the following operations. A protective layer is formed over a substrate, in which the protective layer is formed by a composition including a polymer having a polymer backbone and end groups. The polymer backbone is formed by polymerizing a monomer composition including first monomers, and each of the first monomer independently has an aryl substituted with 1, 2, 3, 4, or 5 hydroxyl groups. The end groups include: or combinations thereof. A is a substituted or unsubstituted hydrocarbon group. B is a hydroxyl group, an alkyl group, or a fluoroalkyl group. A photoresist layer is formed over the protective layer. The photoresist layer is patterned.
    Type: Application
    Filed: May 4, 2023
    Publication date: November 7, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing Hong HUANG, Wei-Han LAI, Ching-Yu CHANG
  • Publication number: 20240369783
    Abstract: A package includes a routing structure including a first waveguide and a photonic device; an electronic die bonded to the routing structure, wherein the electronic die is electrically connected to the photonic device; and an optical coupling structure bonded to the routing structure adjacent the electronic die, wherein the optical coupling structure includes a first lens in a first side of a substrate.
    Type: Application
    Filed: August 11, 2023
    Publication date: November 7, 2024
    Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Chih-Wei Tseng, Jiun Yi Wu
  • Publication number: 20240370631
    Abstract: A system including computer readable storage media including executable instructions and one or more processors configured to execute the executable instructions to obtain a schematic netlist and a performance specification for an integrated circuit, determine electrical constraints for nets in the schematic netlist based on the performance specification, determine physical constraints from the electrical constraints, rout the nets in the schematic netlist based on the electrical constraints and the physical constraints, and provide a data file of a layout.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Hsien Yu Tseng, Guan-Ruei Lu, Wei-Ming Chen, Chih.Chi. Hsiao
  • Publication number: 20240371840
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Publication number: 20240370123
    Abstract: The present disclosure provides a display device. The display device includes a transparent cover plate, a display panel, a frame assembly and an infrared touch assembly. The frame assembly includes an outer frame and a light filtering strip. The light filtering strip is provided with a light filtering part that presses at a front side edge of the transparent cover plate. The outer frame includes an outer frame body, a front frame wall and a rear frame wall. An outer side end of the front frame wall is connected to the outer frame body. An inner side end of the front frame wall presses on a front side surface of the light filtering part. An outer side end of the rear frame wall is connected to the outer frame body. The infrared touch assembly is fixed between the front frame wall and the rear frame wall.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 7, 2024
    Inventors: Jingjing ZHANG, Wei HUANG, Zhaoxi YU, Guangning HAO, Shu ZHANG, Ze JIN, Zhongcheng LI, Wenbo DONG
  • Publication number: 20240370717
    Abstract: A method for a cross-platform distillation framework includes obtaining a plurality of training samples. The method includes generating, using a student neural network model executing on a first processing unit, a first output based on a first training sample. The method also includes generating, using a teacher neural network model executing on a second processing unit, a second output based on the first training sample. The method includes determining, based on the first output and the second output, a first loss. The method further includes adjusting, based on the first loss, one or more parameters of the student neural network model. The method includes repeating the above steps for each training sample of the plurality of training samples.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 7, 2024
    Applicant: Google LLC
    Inventors: Qifei Wang, Yicheng Fan, Wei Xu, Jiayu Ye, Lu Wang, Chuo-Ling Chang, Dana Alon, Erik Nathan Vee, Hongkun Yu, Matthias Grundmann, Shanmugasundaram Ravikumar, Andrew Stephen Tomkins
  • Publication number: 20240370221
    Abstract: An image processor circuit includes a first processor circuit and a second processor circuit. In a two-pixel mode, the first processor circuit is configured to process a first part of first input data and the second processor circuit is configured to process a second part of the first input data to generate output data for a display panel to display. In a picture-in-picture mode, the first processor circuit is configured to process second input data to generate main-picture output data and the second processor circuit is configured to process third input data to generate sub-picture output data for the display panel to display.
    Type: Application
    Filed: November 17, 2023
    Publication date: November 7, 2024
    Inventors: Hui HUANG, Chia-Wei YU, Tien-Hung LIN, Jiamei FENG
  • Publication number: 20240371647
    Abstract: A semiconductor structure includes a die, a molding surrounding the die, and a polymer over the die and the molding. The die has a top surface. The molding has a top surface. The polymer has a first bottom surface contact the die and a second surface contacting the molding. The first bottom surface is at a level substantially same as the second bottom surface.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: YU-HSIANG HU, WEI-YU CHEN, HUNG-JUI KUO, WEI-HUNG LIN, MING-DA CHENG, CHUNG-SHI LIU
  • Publication number: 20240371904
    Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Wei Chuang Wu, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Jhy-Jyi Sze, Keng-Yu Chou, Yen-Ting Chiang, Ming-Hsien Yang, Chun-Yuan Chen
  • Publication number: 20240370222
    Abstract: An image processor circuit includes a first processor circuit and a second processor circuit. In a two-pixel mode, the first processor circuit is configured to process a first part of first input data and the second processor circuit is configured to process a second part of the first input data to generate output data for a display panel to display. The first input data includes K columns, the first part includes 1st to Mth columns of the first input data, and the second part includes Nth to Kth columns of the first input data. N is less than K/2 and M is greater than K/2.
    Type: Application
    Filed: November 17, 2023
    Publication date: November 7, 2024
    Inventors: Hui HUANG, Chia-Wei YU, Tien-Hung LIN, Jiamei FENG
  • Patent number: D1050773
    Type: Grant
    Filed: July 31, 2024
    Date of Patent: November 12, 2024
    Inventor: Wei Yu