Patents by Inventor Wei Yu

Wei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250189795
    Abstract: A mixed reality display device includes a waveguide element, an image light source, a first diffractive optical element lens array and a second diffractive optical element lens array. The image light source is located in the waveguide element. The first diffractive optical element lens array is located on a first side of the waveguide element facing a human eye, the first diffractive optical element lens array includes a plurality of diffractive optical element lenses, and any of the diffractive optical element lenses is configured to converge a light. The second diffractive optical element lens array is located on a second side of the waveguide element opposite to the first side, the second diffractive optical element lens array includes a plurality of diffractive optical element lenses, and any of the diffractive optical element lenses is configured to diverge or converge a light.
    Type: Application
    Filed: May 17, 2024
    Publication date: June 12, 2025
    Inventors: Yeh-Wei YU, Ching-Cherng SUN, Chih-Yuan CHENG, Chih-Hung CHEN, Tsung-Hsun YANG, Shiuan-Huei LIN, Cheng-Chuan LIU
  • Publication number: 20250189796
    Abstract: A mixed reality display device includes a waveguide element, an image display device, an imaging lens, a first diffractive optical element, a first volume holographic optical element, a second volume holographic optical element and a second diffractive optical element. The image display device is configured to emit a light field image. The imaging lens is configured to image an image at infinity. The first diffractive optical element is configured to guide the image into the waveguide element. The first volume holographic optical element and the second volume holographic optical element have an angle selectivity, configured to extract a specific field of view. The second volume holographic optical element has a lens array function to form a light field image source. The second diffractive optical element has a lens array function to transfer the light field image source into a three-dimensional image.
    Type: Application
    Filed: July 29, 2024
    Publication date: June 12, 2025
    Inventors: Yeh-Wei YU, Ching-Cherng SUN, Wen-Kai LIN, Tsung-Hsun YANG, Guan-Yu ZHU, Yu-Chien WANG
  • Patent number: 12327819
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: June 10, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh
  • Publication number: 20250182236
    Abstract: A method for configuring a buffer and an image synthesis apparatus are provided. The image synthesis apparatus includes a memory, and the memory includes a plurality of line buffers. The method includes the following step: dividing, according to a plurality of depths of a plurality of target planes, each of a plurality of target line buffers into a plurality of sections for respectively storing row pixel data of the target planes. The sections correspond to the depths of the target planes, respectively.
    Type: Application
    Filed: June 6, 2024
    Publication date: June 5, 2025
    Inventors: KAI-HSIANG CHOU, CHEN-WEI YU
  • Publication number: 20250181848
    Abstract: Implementations relate to managing multimedia content that is obtained by large language model(s) (LLM(s)) and/or generated by other generative model(s). Processor(s) of a system can: receive natural language (NL) based input that requests multimedia content, generate a response that is responsive to the NL based input, and cause the response to be rendered. In some implementations, and in generating the response, the processor(s) can process, using a LLM, LLM input to generate LLM output, and determine, based on the LLM output, at least multimedia content to be included in the response. Further, the processor(s) can evaluate the multimedia content to determine whether it should be included in the response. In response to determining that the multimedia content should not be included in the response, the processor(s) can cause the response, including alternative multimedia content or other textual content, to be rendered.
    Type: Application
    Filed: February 13, 2025
    Publication date: June 5, 2025
    Inventors: Sanil Jain, Wei Yu, Agoston Weisz, Michael Andrew Goodman, Diana Avram, Amin Ghafouri, Golnaz Ghiasi, Igor Petrovski, Khyatti Gupta, Oscar Akerlund, Evgeny Sluzhaev, Rakesh Shivanna, Thang Luong, Komal Singh, Yifeng Lu, Vikas Peswani
  • Patent number: 12318255
    Abstract: Disclosed are computer-implemented or computer-aided method for diagnosing or predicting the risk of obstructive sleep apnea in a subject. The methods comprise determining whether the subject has obstructive sleep apnea based on at least one quantitative ultrasound parameter and/or at least one morphometric parameter.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: June 3, 2025
    Assignee: AmCad BioMed Corporation
    Inventors: Argon Chen, Yi-li Lee, Pei-Yu Chao, Wei-Hao Chen, Wei-Yu Hsu
  • Publication number: 20250169703
    Abstract: The present invention provides a method and device for obtaining the pressure difference of blood vessels. The method for obtaining the pressure difference of a blood vessel includes: receiving anatomical data of a part of a blood vessel segment, obtaining a geometric model of a target blood vessel according to the anatomical data; obtaining a blood flow model of the target blood vessel and the target blood vessel according to the anatomical data and combining individual data The blood flow velocity V; the geometric model is preprocessed, the cross-sectional morphological model is established, and the shape difference function f(x) of the target blood vessel lumen is calculated, based on the shape difference function f(x) of the target blood vessel lumen And the blood flow velocity V, the pressure difference value ?P at any two positions of the target blood vessel is calculated.
    Type: Application
    Filed: January 16, 2025
    Publication date: May 29, 2025
    Inventors: SHENGXIAN TU, WEI YU, SHUZHAN CHEN, YINGGUANG LI
  • Patent number: 12317547
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.
    Type: Grant
    Filed: July 4, 2023
    Date of Patent: May 27, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Chun-Wei Yu, Yu-Ren Wang
  • Patent number: 12315981
    Abstract: A transmission line device includes a daisy chain structure composed of at least three daisy chain units arranged periodically and continuously. Each of the daisy chain units includes first, second and third conductive lines, and first and second conductive pillars. The first and second conductive lines at a first layer extend along a first direction and are discontinuously arranged. The third conductive line at a second layer extends along the first direction and is substantially parallel to the first and second conductive lines. The first conductive pillar extends in a second direction. The second direction is different from the first direction. A first part of the first conductive pillar is connected to the first and third conductive lines. The second conductive pillar extends in the second direction. A first part of the second conductive pillar is connected to the second and third conductive lines.
    Type: Grant
    Filed: November 25, 2022
    Date of Patent: May 27, 2025
    Assignees: UNIMICRON TECHNOLOGY CORP., NATIONAL TAIWAN UNIVERISTY
    Inventors: Yu-Kuang Wang, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Huang, Wei-Yu Liao, Chi-Min Chang
  • Patent number: 12313511
    Abstract: A method for evaluating the foamability of a test solution. The method includes forming foam in a vertical measurement column including an open top end and a fritted plate proximal to a bottom end by passing a gas stream through the fitted plate and through the test solution present in the vertical measurement column at a gas volume rate (GVR) and a gas flow rate (GFR). The foam travels upwards in the vertical measurement column while the gas stream is passing through the test solution. The method further includes measuring the viscosity of the foam with a vibration viscometer disposed proximal to the top end of the vertical measurement column, and further recording a plurality of vibration viscometer measurement results and storing the results (a surfactant amount Csurf, the GVR, and the GFR) in memory to determine one or more foam properties of the test solution.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: May 27, 2025
    Assignee: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS
    Inventors: Wei Yu, Hau Yung Lo, Zhengwei Pan, Mazen Yousef Kanj
  • Patent number: 12315730
    Abstract: A method includes providing a structure having a substrate, a semiconductor channel layer over the substrate, an interfacial oxide layer over the semiconductor channel layer, and a high-k gate dielectric layer over the interfacial oxide layer, wherein the semiconductor channel layer includes germanium. The method further includes forming a metal nitride layer over the high-k gate dielectric layer and performing a first treatment to the structure using a metal-containing gas. After the performing of the first treatment, the method further includes depositing a silicon layer over the metal nitride layer; and then annealing the structure such that a metal intermixing layer is formed over the high-k gate dielectric layer. The metal intermixing layer includes a metal oxide having metal species from the high-k gate dielectric layer and additional metal species from the metal-containing gas.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: May 27, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chandrashekhar Prakash Savant, Kin Shun Chong, Tien-Wei Yu, Chia-Ming Tsai
  • Patent number: 12299766
    Abstract: Systems and methods for supporting generic pointers in hardware of a graphics processing unit (GPU) are provided. In various examples, a GPU includes multiple sub-cores each having a processing resource and a load/store pipeline. The processing resource is operable to receive a memory access message including a pointer and a memory type identifier indicative of the pointer representing a generic pointer. The processing resource is further operable to output a load or store operation to the load/store pipeline based on the memory access message, including computing an address for the load or store operation by adding a base address of a named memory type of a plurality of named memory types referenced by the generic pointer to an offset into a memory of the named memory type. The load/store pipeline is operable to, responsive to receipt of the load or store operation, access the memory at the address.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 13, 2025
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Prathamesh Raghunath Shinde, Ben J. Ashbaugh, Wei-Yu Chen, Abhishek R. Appu, Vasanth Ranganathan, Dmitry Yurievich Babokin, Ankur N. Shah
  • Publication number: 20250149488
    Abstract: In an embodiment, a method includes forming a device region along a first substrate; forming an interconnect structure over the device region and the first substrate; forming a metal pillar over the interconnect structure, forming the metal pillar comprising: forming a base layer over the interconnect structure; forming an intermediate layer over the base layer; and forming a capping layer over the intermediate layer; forming a solder region over the capping layer; and performing an etch process to recess sidewalls of the base layer and the capping layer from sidewalls of the intermediate layer and the solder region.
    Type: Application
    Filed: February 23, 2024
    Publication date: May 8, 2025
    Inventors: Wei-Yu Chen, Chao-Wei Chiu, Hsin Liang Chen, Hao-Jan Shih, Hao-Jan Pei, Hsiu-Jen Lin
  • Publication number: 20250139379
    Abstract: Implementations relate to generating multi-modal response(s) through utilization of large language model(s) (LLM(s)) and other generative model(s). Processor(s) of a system can: receive natural language (NL) based input, generate a multi-modal response that is responsive to the NL based output, and cause the multi-modal response to be rendered. In some implementations, and in generating the multi-modal response, the processor(s) can process, using a LLM, LLM input to generate LLM output, and determine, based on the LLM output, textual content and generative multimedia content for inclusion in the multi-modal response. In some implementations, the generative multimedia content can be generated by another generative model (e.g., an image generator, a video generator, an audio generator, etc.) based on generative multimedia content prompt(s) included in the LLM output and that is indicative of the generative multimedia content.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 1, 2025
    Inventors: Sanil Jain, Wei Yu, Alessandro Agostini, Agoston Weisz, Michael Andrew Goodman, Attila Dankovics, Elle Chae, Evgeny Sluzhaev, Amin Ghafouri, Golnaz Ghiasi, Igor Petrovski, Konstantin Shagin, Marcelo Menegali, Oscar Akerlund, Rakesh Shivanna, Thang Luong, Tiffany Chen, Vikas Peswani, Yifeng Lu
  • Publication number: 20250135391
    Abstract: Systems and methods for extracting components from a gas. A chamber to collect water and another chamber to collect carbon dioxide from a gas are each configured with topologically optimized sorbents. A DAC method for extracting components from a gas includes water and carbon dioxide chambers configured with topologically optimized sorbents to respectively capture water and carbon dioxide.
    Type: Application
    Filed: October 25, 2024
    Publication date: May 1, 2025
    Applicant: Omega Dac Inc.
    Inventors: Jijun Miao, Wei Yu, Michael R. Berry
  • Publication number: 20250134460
    Abstract: An earbud with temperature sensing is provided, and the earbud includes a housing and a first temperature sensor. The housing defines a second opening and a third opening. The first temperature sensor is positioned along an interior surface of the housing and aligned with the second opening in the housing for non-contact temperature sensing. In response to the earbud being positioned for use within an ear of a user, the second opening aligns with an inner side of the tragus close to the ear canal, the cavum conchae, an inner edge of the antitragus, or the cheek close to the ear, such that the first temperature sensor detects a body temperature of the user through the second opening.
    Type: Application
    Filed: January 2, 2025
    Publication date: May 1, 2025
    Inventors: WEI-LUN SUNG, PO-WEI YU, CHIH-MING SUN
  • Publication number: 20250140757
    Abstract: A chip package structure is provided. The chip package structure includes a wiring structure. The chip package structure includes a first chip structure over the wiring structure. The chip package structure includes a first molding layer surrounding the first chip structure. The chip package structure includes a second chip structure over the first chip structure and the first molding layer. The chip package structure includes a second molding layer surrounding the second chip structure and over the first chip structure and the first molding layer. The chip package structure includes a third chip structure over the second chip structure and the second molding layer. The chip package structure includes a third molding layer surrounding the third chip structure and over the second chip structure and the second molding layer. The chip package structure includes a fourth molding layer surrounding the second molding layer and the third molding layer.
    Type: Application
    Filed: December 31, 2024
    Publication date: May 1, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yu CHEN, An-Jhih SU
  • Patent number: 12288721
    Abstract: A method includes etching a semiconductor substrate to form a trench between a first semiconductor strip and a second semiconductor strip. The first semiconductor strip has a first width at about 5 nm below a top of the first semiconductor strip and a second width at about 60 nm below the top of the first semiconductor strip. The first width is smaller than about 5 nm, and the second width is smaller than about 14.5 nm. The trench is filled with dielectric materials to form an isolation region, which is recessed to have a depth. A top portion of the first semiconductor strip protrudes higher than the isolation region to form a protruding fin. The protruding fin has a height smaller than the depth. A gate stack is formed to extend on a sidewall and a top surface of the protruding fin.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Ming-Feng Hsieh, Hsueh-Chang Sung, Pei-Ren Jeng, Yee-Chia Yeo, Chien-Chia Cheng
  • Lid
    Patent number: D1072561
    Type: Grant
    Filed: September 25, 2024
    Date of Patent: April 29, 2025
    Assignee: Foshan Jiuzhou Technology Co., Ltd.
    Inventor: Wei Yu
  • Patent number: D1075127
    Type: Grant
    Filed: January 12, 2025
    Date of Patent: May 13, 2025
    Inventor: Wei Yu