Patents by Inventor Wei Yu

Wei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240147419
    Abstract: Provided in the present disclosure are a paging method and apparatus, and a storage medium. The paging method includes: determining that entry into a target sleep state is required, and transmitting an assisted paging request to at least one second terminal device; and determining that a target terminal device of the at least one second terminal device accepts the assisted paging request, and entering the target sleep state.
    Type: Application
    Filed: February 24, 2021
    Publication date: May 2, 2024
    Applicant: BEIJING XIAOMI MOBILE SOFTWARE CO., LTD.
    Inventors: Xiaowei JIANG, Wei HONG, Dong CHEN, Lei YU
  • Publication number: 20240141123
    Abstract: A manufacturing method of a modified polymer layer modified by hydroxyapatite is provided in the present disclosure, including following steps: (a) providing a polymer layer; (b) plasma-activating acrylic acid using an atmospheric cold plasma device to modify a surface of the polymer layer to obtain an acrylic-modified polymer layer; (c) immersing the acrylic-modified polymer layer in a first solution containing a calcium ion to obtain a calcium-containing modified layer; and (d) immersing the calcium-containing modified layer in a second solution containing phosphate salt to obtain a modified polymer layer modified by hydroxyapatite.
    Type: Application
    Filed: June 9, 2023
    Publication date: May 2, 2024
    Inventors: Wei-Yu CHEN, Jui-Sheng LEE, Hui-Ju HSU
  • Publication number: 20240146286
    Abstract: An integrated circuit includes a first inverter, a first transmission gate, and a second inverter constructed with wide type-one transistors and wide type-two transistors. The integrated circuit also includes a first clocked inverter and a second clocked inverter constructed with narrow type-one transistors and narrow type-two transistors. A master latch is formed with the first inverter and the first clocked inverter. A slave latch is formed with the second inverter and the second clocked inverter. The first transmission gate is coupled between the master latch and the slave latch. The wide type-one transistors are formed in a wide type-one active-region structure and the narrow type-one transistors are formed in a narrow type-one active-region structure. The wide type-two transistors are formed in a wide type-two active-region structure and the narrow type-two transistors are formed in in a narrow type-two active-region structure.
    Type: Application
    Filed: January 27, 2023
    Publication date: May 2, 2024
    Inventors: Ching-Yu HUANG, Jiann-Tyng TZENG, Wei-Cheng LIN
  • Publication number: 20240143657
    Abstract: Embodiments of this specification disclose graph data partition computer-implemented methods, non-transitory, computer-readable media, and computer-implemented systems. A computer-implemented method includes partitioning vertices in graph data into a plurality of dataset. Edges in the graph data are partitioned into datasets that include target vertices of the edges, where the datasets are used by nodes in a distributed cluster to perform graph computation, and where computational loads of the plurality of datasets are similar Implementations of this specification can achieve load balancing between nodes in the distributed cluster and can reduce communication overhead.
    Type: Application
    Filed: December 22, 2023
    Publication date: May 2, 2024
    Applicant: ALIPAY (HANGZHOU) INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Wei Qin, Jiping Yu, Xiaowei Zhu, Wenguang Chen
  • Publication number: 20240146945
    Abstract: Provided is a method for video decoding including: receiving a control variable enabling adaptive switch between motion vector refinement (MVR) offset sets; receiving an indication variable enabling adaptive switch between codeword tables that binarize offset magnitudes in the MVR offset sets under the coding level; partitioning the video block into a first and a second geometric partition; selecting an MVR offset set based on the control variable; receiving syntax elements to determine a first and second MVR offsets applied to the first and second geometric partitions from the selected MVR offset set; obtaining a first and second MVs from a candidate list for the first and the second geometric partition; calculating a first and second refined MVs based on the first and second MVs and the first and second MVR offsets; and obtaining prediction samples based on the first and second refined MVs.
    Type: Application
    Filed: December 14, 2023
    Publication date: May 2, 2024
    Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Xiaoyu XIU, Wei CHEN, Che-Wei KUO, Hong-Jheng ZHU, Ning YAN, Yi-wen CHEN, Xianglin WANG, Bing YU
  • Publication number: 20240144050
    Abstract: A two-stage machine learning model is used to for categorization of a dataset, such as transactions. A plurality of complementary base machine learning models are used to generate initial inference results and associated measures of inference confidence from the dataset, which are collected as a meta dataset. Each of the complementary models is associated with a different part of the dataset in which it has a higher accuracy in that part than the other models. The meta dataset is provided as input to a meta machine learning model, which is trained to produce a final inference result, and a confidence score model, which is trained to produce a confidence score associated with the final inference result.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 2, 2024
    Applicant: Intuit Inc.
    Inventors: Wei Wang, Mu Li, Yue Yu, Kun Lu, Rohini R. Mamidi, Nazanin Zaker Habibabadi, Selvam Raman
  • Publication number: 20240144428
    Abstract: An image processing circuit includes a receiving circuit, a transmitting circuit, a first asynchronous handshake circuit, a super resolution scale-up model and a second asynchronous handshake circuit. The receiving circuit is arranged to receive an input image with a first pixel clock frequency. The first asynchronous handshake circuit is arranged to receive the input image from the receiving circuit according to a receiving timing. The super resolution scale-up model is arranged to scale up the input image to generate an output image with a second pixel clock frequency. The second asynchronous handshake circuit is arranged to output the output image to the transmitting circuit according to a transmitting timing to transmit the output image, wherein the first asynchronous handshake circuit, the super resolution scale-up model, and the second asynchronous handshake circuit operate at a clock frequency independent of the first pixel clock frequency and the second pixel clock frequency.
    Type: Application
    Filed: June 28, 2023
    Publication date: May 2, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Tien-Hung Lin, Chia-Wei Yu, Yi-Ting Bao
  • Publication number: 20240144426
    Abstract: A super resolution (SR) image generation circuit includes an image scale-up circuit, a stable SR processing circuit, a generative adversarial network (GAN) processing circuit, and a configurable basic block pool circuit. The image scale-up circuit is arranged to receive and process an input image to generate a scaled-up image. The stable SR processing circuit is arranged to receive a feature map of the input image to generate a stable delta value. The GAN processing circuit is arranged to receive the feature map to generate a GAN delta value. The configurable basic block pool circuit is arranged to dynamically configure a plurality of basic blocks according to a depth requirement of the input image, to generate a configuration result. The SR image generation circuit generates an SR image according to the scaled-up image, the stable delta value, and the GAN delta value.
    Type: Application
    Filed: April 20, 2023
    Publication date: May 2, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Shang-Yen Lin, Yi-Ting Bao, HAO-RAN WANG, Chia-Wei Yu
  • Publication number: 20240145460
    Abstract: An integrated circuit includes a T-coil circuit, a silicon-controlled rectifier (SCR), and a signal-loss prevention circuit. The T-coil circuit is coupled to an input/output (I/O) pad and an internal circuit. The SCR is coupled to the T-coil circuit and the internal circuit. The signal-loss prevention circuit is coupled to the T-coil circuit and the SCR. The signal-loss prevention circuit includes a resistor coupled to the T-coil circuit and the SCR. An electrostatic current flows through the resistor and turns on the SCR. The signal-loss prevention circuit may also include a diode circuit coupled to the T-coil circuit and the SCR. The diode circuit is configured to prevent signal loss.
    Type: Application
    Filed: January 3, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Min WU, Ming-Dou KER, Chun-Yu LIN, Li-Wei CHU
  • Publication number: 20240145327
    Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.
    Type: Application
    Filed: December 27, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Jung Hsueh, Cheng-Nan Lin, Wan-Yu Chiang, Wei-Hung Lin, Ching-Wen Hsiao, Ming-Da Cheng
  • Publication number: 20240145581
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Chu LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
  • Patent number: 11973895
    Abstract: Embodiments of this application disclose a call method and an apparatus. In the call method, when a user does not actively select an audio device as a voice pickup device and a voice play device, after establishing a call connection to another electronic device, an electronic device selects, from available audio devices, an audio device that meets a user expectation as the voice pickup device and the voice play device. According to technical solutions provided in the embodiments of this application, user experience in a call process can be improved.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: April 30, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Fusheng Li, Shengfeng Zhou, Yi Yu, Wei Yuan
  • Patent number: 11973338
    Abstract: A chip-level software and hardware cooperative relay protection device is provided. The device includes: a control chip, wherein a first control unit, a second control unit, and multiple logic circuits are integrated on the control chip; and the logic circuits perform microsecond-level rapid calculation on electrical signals of a protected electrical device, obtain fault feature parameters of the protected electrical device are and transmit same to the first control unit, then perform millisecond-level real-time protection logic determination according to the fault feature parameters of the protected electrical device to obtain relay protection results of the protected electrical device, and protect the protected electrical device by controlling an external relay according to the relay protection results.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: April 30, 2024
    Assignee: DIGITAL GRID RES. INST., CHINA SOUTHERN PWR. GRID
    Inventors: Peng Li, Wei Xi, Xiaobo Li, Hao Yao, Yang Yu, Tiantian Cai, Junjian Chen
  • Patent number: 11972587
    Abstract: An establishing method of semantic distance map for a moving device, includes capturing an image; obtaining a single-point distance measurement result of the image; performing recognition for the image to obtain a recognition result of each obstacle in the image; and determining a semantic distance map corresponding to the image according to the image, the single-point distance measurement result and the recognition result of each obstacle of in the image; wherein each pixel of the semantic distance map includes an obstacle information, which includes a distance between the moving device and an obstacle, a type of the obstacle, and a recognition probability of the obstacle.
    Type: Grant
    Filed: May 22, 2022
    Date of Patent: April 30, 2024
    Assignee: FITIPOWER INTEGRATED TECHNOLOGY INC.
    Inventors: Hsueh-Tse Lin, Wei-Hung Hsu, Shang-Yu Yeh
  • Patent number: 11972537
    Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: April 30, 2024
    Assignee: YU JUNG CHANG TECHNOLOGY CO., LTD.
    Inventors: Chih-Chuan Chen, Wei-Hsiang Tsai, Chin-Yu Chen, Ching-Cherng Sun, Jann-Long Chern, Yu-Kai Lin
  • Patent number: 11973664
    Abstract: The disclosure reveals a system and approach for remote health monitoring and diagnostics of room controllers, networks and devices. A master room controller may be used to open a system health page or a diagnostic page for other controllers. A system health page may provide an overview of virtually all of the other room controllers. A tool of the present system may be used to trouble shoot issues remotely at another room controller in lieu of doing a visit to the respective room controller. A user may navigate from the system health page to virtually any place on the room controller to diagnose issues. The navigation may be done by hyper linking from the system health page. The healthy controllers may be hidden from the page so that the unhealthy systems can be viewed in one shot.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: April 30, 2024
    Assignee: HONEYWELL INTERNATIONAL INC.
    Inventors: Ajay Nair, Upender Paravastu, Jijji Ramanathan, Mallikarjuna Nonayinakere Sugandharajappa, James Barrette, Liwen Yu, Christopher Martin, Wei Hua, Robert Klamka
  • Publication number: 20240134160
    Abstract: The present disclosure provides an image capturing optical system comprising: a positive first lens element having a convex object-side surface; a negative second lens element having a concave object-side surface; a third lens element; a fourth lens element having a convex object-side surface and a concave image-side surface, the object-side surface and the image-side surface thereof being aspheric; a fifth lens element having a concave image-side surface concave, both of the object-side surface and the image-side surface being aspheric, at least one of the object-side surface and the image-side surface having at least one convex shape in an off-axis region thereof.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 25, 2024
    Inventors: Kuan-Ming CHEN, Wei-Yu CHEN
  • Publication number: 20240134279
    Abstract: A photoresist includes a solvent, a polymer and an additive. The polymer is dissolved in the solvent, and the additive is dispersed in the solvent. The additive includes a double bond or includes an epoxy group. The additive has a surface tension different from a surface tension of the polymer.
    Type: Application
    Filed: March 27, 2023
    Publication date: April 25, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Hsin HSIEH, Wei-Han LAI, Ching-Yu CHANG
  • Publication number: 20240134881
    Abstract: Embodiments of this specification provide distributed data processing methods, apparatuses, and devices. One method includes: determining an active vertex set that currently participates in data processing in target graph data, in response to determining that an external memory of a first distributed node stores an active vertex in the active vertex set, determining, from a plurality of predetermined data processing modes, a target data processing mode that matches the active vertex set, determining, based on the target data processing mode, a to-be-updated vertex according to the association relationship with the active vertex, and sending, based on first data of the active vertex in the external memory, a first update message to a target distributed node in which the to-be-updated vertex is located.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 25, 2024
    Applicant: Alipay (Hangzhou) Information Technology Co., Ltd.
    Inventors: Wei Qin, Jiping Yu, Xiaowei Zhu, Wenguang Chen
  • Publication number: 20240134163
    Abstract: An image capturing lens assembly includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, and a sixth lens element. The first lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The second and third lens elements have refractive power. The fourth lens element has positive refractive power. The fifth lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof. The sixth lens element with refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The image capturing lens assembly has a total of six lens elements with refractive power.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 25, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Cheng-Chen LIN, Wei-Yu CHEN