Patents by Inventor Wei Yu

Wei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085669
    Abstract: An optical imaging lens assembly includes seven lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. The seventh lens element has an image-side surface being concave in a paraxial region thereof. At least one of an object-side surface and the image-side surface of the seventh lens element has at least one critical point in an off-axis region thereof. The object-side surface and the image-side surface of the seventh lens element are both aspheric.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventor: Wei-Yu CHEN
  • Publication number: 20240088062
    Abstract: A package structure includes a die, an encapsulant laterally encapsulating the die, a warpage control material disposed over the die, and a protection material disposed over the encapsulant and around the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
  • Publication number: 20240077726
    Abstract: A display device is configured to determine a target location. The display device includes a waveguide element, a display panel and a processor. The waveguide element is configured to receive an image and reflect the image to an eyeball location. The display panel is located at one side of the waveguide element. The display panel has a plurality of pixel units. The display panel is located between the waveguide element and the target location. The processor is electrically connected to the display panel. The processor is configured to determine the pixel units in a blocking area of the display panel to be opaque. The blocking area of the display panel overlaps the target location. The display panel displays the pixel units in the blocking area as grayscale according to the processor.
    Type: Application
    Filed: November 29, 2022
    Publication date: March 7, 2024
    Inventors: Yeh-Wei YU, Ko-Ting CHENG, Pin-Duan HUANG, Ching-Cherng SUN
  • Publication number: 20240076980
    Abstract: Systems and methods for simulating subterranean regions having multi-scale, complex fracture geometries in a realistic simulation environment, which includes in the modeling process three-dimensional multi-scale rock discontinuities, hydraulic fractures, and heterogenous reservoir properties. Non-intrusive embedded discrete fracture modeling formulations are applied in conjunction with commercial or in-house simulators to efficiently and accurately model subsurface characteristics including three-dimensional geometries having combinations of complex hydraulic fractures and multi-scale rock discontinuities.
    Type: Application
    Filed: September 4, 2022
    Publication date: March 7, 2024
    Applicants: PetroChina Southwest Oil & Gas Field Company, ZFRAC LLC, BJ Karst Science & Technology Ltd.
    Inventors: Rui Yong, Jianfa Wu, Joseph Alexander Leines Artieda, Cheng Chang, Jijun Miao, Wei Yu, Hongbing Xie
  • Publication number: 20240072021
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Publication number: 20240071888
    Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.
    Type: Application
    Filed: August 28, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chang Lin, Yen-Fu Su, Chin-Liang Chen, Wei-Yu Chen, Hsin-Yu Pan, Yu-Min Liang, Hao-Cheng Hou, Chi-Yang Yu
  • Publication number: 20240071881
    Abstract: A semiconductor device assembly includes a semiconductor die and a substrate coupled to the semiconductor die. The substrate includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the second solder mask layer through the secondary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Ling Pan, Wei Yu, Kelvin Tan Aik Boo
  • Publication number: 20240071901
    Abstract: A capacitor structure including a substrate, an insulating layer, a capacitor, a shielding layer, a first connection terminal, and a second connection terminal is disposed. The insulating layer is disposed on the substrate. The capacitor includes a first electrode layer, a second electrode layer, a dielectric layer. The first electrode layer is disposed on the insulating layer. The second electrode layer is disposed on the first electrode layer. The dielectric layer is disposed between the first electrode layer and the second electrode layer. The shielding layer is disposed in the insulating layer. The shielding layer is located between the first electrode layer and the substrate. The first connection terminal is electrically connected to the first electrode layer. The second connection terminal is electrically connected to the second electrode layer.
    Type: Application
    Filed: September 21, 2022
    Publication date: February 29, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Wei-Yu Lin
  • Publication number: 20240063130
    Abstract: A package structure including a redistribution circuit structure, a wiring substrate, a conductive pillar and a solder material is provided. The redistribution circuit structure has a first surface and a second surface opposite to the first surface and includes a first insulating layer and a first redistribution pattern in the insulating layer. The first redistribution pattern comprises a first contact pad disposed at the first surface. The wiring substrate is disposed opposite the first surface of the redistribution circuit structure and includes a second insulating layer and a second redistribution pattern in the second insulating layer. The second redistribution pattern comprises a second contact pad. The conductive pillar is disposed between the first contact pad and the second contact pad. The solder material disposed between the conductive pillar and the second contact pad.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Yu-Min Liang, Chien-Hsun Lee
  • Publication number: 20240061216
    Abstract: A photographing lens assembly includes a total of eight lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element and an eighth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof. The second lens element has negative refractive power. The eighth lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof. At least one lens element of the photographing lens assembly has at least one lens surface having at least one inflection point.
    Type: Application
    Filed: October 24, 2023
    Publication date: February 22, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Chun-Che HSUEH, Hung-Shuo CHEN, Kuan Chun WANG, Wei-Yu CHEN
  • Publication number: 20240060867
    Abstract: A method for evaluating the foamability of a test solution. The method includes forming foam in a vertical measurement column including an open top end and a fritted plate proximal to a bottom end by passing a gas stream through the fitted plate and through the test solution present in the vertical measurement column at a gas volume rate (GVR) and a gas flow rate (GFR). The foam travels upwards in the vertical measurement column while the gas stream is passing through the test solution. The method further includes measuring the viscosity of the foam with a vibration viscometer disposed proximal to the top end of the vertical measurement column, and further recording a plurality of vibration viscometer measurement results and storing the results (a surfactant amount Csurf, the GVR, and the GFR) in memory to determine one or more foam properties of the test solution.
    Type: Application
    Filed: February 14, 2023
    Publication date: February 22, 2024
    Applicant: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS
    Inventors: Wei YU, Hau Yung LO, Zhengwei PAN, Mazen Yousef KANJ
  • Publication number: 20240062957
    Abstract: A capacitor unit includes a substrate; an insulation layer formed on the substrate; a capacitor stacking structure formed on the insulation layer, and having a first bonding pad, a first conductive portion, a second bonding pad and a second conductive portion; and a first metallic wall and a second metallic wall formed on two opposite sides of the capacitor stacking structure. A capacitor integrated structure includes a wafer; a plurality of capacitor stacking structures arrayed in X-axis direction and Y-axis direction of the wafer to form a matrix on the wafer; a plurality of metallic dividers provided in the X-axis direction of the wafer between adjacent ones of the capacitor stacking structures; and a plurality of insulation dividers provided in the Y-axis direction of the wafer between adjacent ones of the capacitor stacking structures.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Inventors: WEI-YU LIN, KUO-YU YEH
  • Publication number: 20240061217
    Abstract: An optical lens system includes nine lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element, an eighth lens element and a ninth lens element. At least one lens surface of the seventh lens element, the eighth lens element and the ninth lens element has at least one critical point in an off-axis region thereof, and each of the seventh lens element, the eighth lens element and the ninth lens element has at least one lens surface being aspheric.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventor: Wei-Yu CHEN
  • Patent number: 11908884
    Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chou, Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Huang-Wen Tseng, Chwen-Ming Liu
  • Patent number: 11908915
    Abstract: A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shahaji B. More, Chandrashekhar Prakash Savant, Tien-Wei Yu, Chia-Ming Tsai
  • Patent number: 11910257
    Abstract: Apparatus and methods are provided for RRM measurement in the NR network. In one novel aspect, the RRM measurement is configured with one measurement gap for SS block and CSI-RS. In one embodiment, an extended MGL (eMGL) is configured such that the SS block and CSI-RS is measurement within one measurement gap. In another embodiment, the shorter MGL (sMGL) that is shorter than the standard MGL is configured. In another novel aspect, the CSI-RS is allocated adjacent to the SS blocks such that one measurement gap is configured for both the SS block and CSI-RS measurement. In another novel aspect, the CSI-RS measurement is conditionally configured. In yet another novel aspect, the UE decodes the time index of the SS block conditionally.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: February 20, 2024
    Inventors: Din-Hwa Huang, Hsuan-Li Lin, Tsang-Wei Yu, Yih-Shen Chen, Chiao Yao Chuang
  • Patent number: 11907674
    Abstract: Implementations relate to generating multi-modal response(s) through utilization of large language model(s) (LLM(s)). Processor(s) of a system can: receive natural language (NL) based input, generate a multi-modal response that is responsive to the NL based output, and cause the multi-modal response to be rendered. In some implementations, and in generating the multi-modal response, the processor(s) can process, using a LLM, LLM input (e.g., that includes at least the NL based input) to generate LLM output, and determine, based on the LLM output, textual content for inclusion in the multi-modal response and multimedia content for inclusion in the multi-modal response. In some implementations, the multimedia content can be obtained based on a multimedia content tag that is included in the LLM output and that is indicative of the multimedia content. In various implementations, the multimedia content can be interleaved between segments of the textual content.
    Type: Grant
    Filed: September 20, 2023
    Date of Patent: February 20, 2024
    Assignee: GOOGLE LLC
    Inventors: Oscar Akerlund, Evgeny Sluzhaev, Golnaz Ghiasi, Thang Luong, Yifeng Lu, Igor Petrovski, Ágoston Weisz, Wei Yu, Rakesh Shivanna, Michael Andrew Goodman, Apoorv Kulshreshtha, Yu Du, Amin Ghafouri, Sanil Jain, Dustin Tran, Vikas Peswani, YaGuang Li
  • Patent number: 11906714
    Abstract: A photographing optical lens assembly includes seven lens elements, which are, in order from an object side to an image side along an optical path: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. The first lens element has negative refractive power. The third lens element with positive refractive power has an image-side surface being convex in a paraxial region thereof. The fifth lens element has an object-side surface being concave in a paraxial region thereof. The sixth lens element has an object-side surface being convex in a paraxial region thereof. The seventh lens element has an image-side surface being concave in a paraxial region thereof and having at least one convex critical point in an off-axis region thereof.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: February 20, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Kuo-Jui Wang, Cheng-Chen Lin, Wei-Yu Chen
  • Patent number: 11908742
    Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a semiconductor substrate, a first fin and a second fin extending from the semiconductor substrate, a first lower semiconductor feature over the first fin, a second lower semiconductor feature over the second fin. Each of the first and second lower semiconductor features includes a top surface bending downward towards the semiconductor substrate in a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins. The semiconductor device also includes an upper semiconductor feature over and in physical contact with the first and second lower semiconductor features, and a dielectric layer on sidewalls of the first and second lower semiconductor features.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Tsz-Mei Kwok, Ming-Hua Yu
  • Patent number: D1017230
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: March 12, 2024
    Inventor: Wei Yu