Abstract: A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 ? to 300 ?, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 ? to 3000 ?, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about ?4V to ?5V, having a pulse width of between about 75 nsec to 1 ?sec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 ?sec.

Abstract: A RRAM memory cell is formed on a silicon substrate having a operative junction therein and a metal plug formed thereon, includes a first oxidation resistive layer; a first refractory metal layer; a CMR layer; a second refractory metal layer; and a second oxidation resistive layer. A method of fabricating a multi-layer electrode RRAM memory cell includes preparing a silicon substrate; forming a junction in the substrate taken from the group of junctions consisting of N+ junctions and P+ junctions; depositing a metal plug on the junction; depositing a first oxidation resistant layer on the metal plug; depositing a first refractory metal layer on the first oxidation resistant layer; depositing a CMR layer on the first refractory metal layer; depositing a second refractory metal layer on the CMR layer; depositing a second oxidation resistant layer on the second refractory metal layer; and completing the RRAM memory cell.

Abstract: A low-capacitance one-resistor/one-diode (1R1D) R-RAM array with a floating p-well is provided. The fabrication method comprises: forming an integrated circuit (IC) substrate; forming an n-doped buried layer (buried n layer) of silicon overlying the substrate; forming n-doped silicon sidewalls overlying the buried n layer; forming a p-doped well of silicon (p-well) overlying the buried n layer; and, forming a 1R1D R-RAM array overlying the p-well. Typically, the combination of the buried n layer and the n-doped sidewalls form an n-doped well (n-well) of silicon. Then, the p-well is formed inside the n-well. In other aspects, the p-well has sidewalls, and the method further comprises: forming an oxide insulator overlying the p-well sidewalls, between the n-well and the R-RAM array.

Abstract: A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.

Abstract: A drain loaded 1T1R resistive memory device and 1T1R resistive memory array are provided. The resistive memory array comprises an array of drain loaded 1T1R resistive memory device structures. Word lines are connected across transistor gates, while a resistive elements are connected between transistor gates and bit lines. The resistive element comprises a material with a resistance that is changed electrically, for example using a sequence of electric pulses. The resistive element may comprise PCMO.

Abstract: Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation.

Abstract: A method of forming a perovskite thin film includes preparing a perovskite precursor solution; preparing a silicon substrate for deposition of a perovskite thin film, including forming a bottom electrode on the substrate; securing the substrate in a spin-coating apparatus and spinning the substrate at a predetermined spin rate; injecting a perovskite precursor solution into the spin-coating apparatus thereby coating the substrate with the perovskite precursor solution to form a coated substrate; baking the coated substrate at temperatures which increase incrementally from about 90° C. to 300° C.; and annealing the coated substrate at a temperature of between about 500° C. to 800° C. for between five minutes to fifteen minutes.

Abstract: Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.

Abstract: A method of applying a PCMO thin film on an iridium substrate for use in a RRAM device, includes preparing a substrate; depositing a barrier layer on the substrate; depositing a layer of iridium on the barrier layer; spin coating a layer of PCMO on the iridium; baking the PCMO and substrate in a three-step baking process; post-bake annealing the substrate and the PCMO in a RTP chamber; repeating said spin coating, baking and annealing steps until the PCMO has a desired thickness; annealing the substrate and PCMO; depositing a top electrode; and completing the RRAM device.

Abstract: A single solution MOCVD precursor is provided for depositing PCMO. An MOCVD process is provided for controlling the composition of PCMO by determining the deposition rate of each metal component within the precursor solution and determining the molar ratio of the metals based on the deposition rates of each within the temperature ranges for substrate temperature and vaporizer temperature, and the composition of PCMO to be deposited. The composition of the PCMO is further controlled by adjusting the substrate temperature, the vaporizer temperature or both.

Abstract: A low-capacitance one-resistor/one-diode (1R1D) R-RAM array with a floating p-well is provided. The fabrication method comprises: forming an integrated circuit (IC) substrate; forming an n-doped buried layer (buried n layer) of silicon overlying the substrate; forming n-doped silicon sidewalls overlying the buried n layer; forming a p-doped well of silicon (p-well) overlying the buried n layer; and, forming a 1R1D R-RAM array overlying the p-well. Typically, the combination of the buried n layer and the n-doped sidewalls form an n-doped well (n-well) of silicon. Then, the p-well is formed inside the n-well. In other aspects, the p-well has sidewalls, and the method further comprises: forming an oxide insulator overlying the p-well sidewalls, between the n-well and the R-RAM array.

Abstract: Low cross talk resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises a bit formed using a perovskite material interposed at a cross point of an upper electrode and lower electrode. Each bit has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit, decrease the resistivity of the bit, or determine the resistivity of the bit. Memory circuits are provided to aid in the programming and read out of the bit region.

Abstract: A method of forming a PCMO thin film in a RRAM device includes preparing a substrate; depositing a metal barrier layer on the substrate; forming a bottom electrode on the barrier layer; spin-coating a layer of Pr1−xCaxMnO3 (PCMO) on the bottom electrode using a PCMO precursor; baking the PCMO thin film in one or more baking steps; annealing the PCMO thin film in a first annealing step after each spin-coating step; repeating the spin-coating step, the baking step and the first annealing step until the PCMO thin film has a desired thickness; annealing the PCMO thin film in a second annealing step, thereby producing a PCMO thin film having a crystalline structure of Pr1−xCaxMnO3, where 0.2<=X<=0.5; depositing a top electrode; patterning the top electrode; and completing the RRAM device.

Abstract: A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.

Abstract: A memory array dual-trench isolation structure and a method for forming the same have been provided.

Abstract: A method of preparing a hafnium nitrate thin film includes placing phosphorus pentoxide in a first vessel; connecting the first vessel to a second vessel containing hafnium tetrachloride; cooling the second vessel with liquid nitrogen; dropping fuming nitric acid into the first vessel producing N2O5 gas; allowing the N2O5 gas to enter the second vessel; heating the first vessel until the reaction is substantially complete; disconnecting the two vessels; removing the second vessel from the liquid nitrogen bath; heating the second vessel; refluxing the contents of the second vessel; drying the compound in the second vessel by dynamic pumping; purifying the compound in the second vessel by sublimation to form Hf(NO3)4, and heating the Hf(NO3)4 to produce HfO2 for use in an ALCVD process.

Abstract: A method for chemical vapor deposition of copper metal thin film on a substrate includes heating a substrate onto which the copper metal thin film is to be deposited in a chemical vapor deposition chamber; vaporizing a precursor containing the copper metal, wherein the precursor is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene; introducing the vaporized precursor into the chemical vapor deposition chamber adjacent the heated substrate; and condensing the vaporized precursor onto the substrate thereby depositing copper metal onto the substrate. A copper metal precursor for use in the chemical vapor deposition of a copper metal thin film is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene taken from the group of alkenes consisting of 1-pentene, 1-hexene and trimethylvinylsilane.

Abstract: A method of fabricating a variable resistance device, wherein the resistance is changed by passing a voltage of various pulse length through the device, includes preparing a silicon substrate; forming a silicon oxide layer on the substrate; depositing a first metal layer on the silicon oxide, wherein the metal of the first metal layer is taken from the group of metals consisting of platinum and iridium; depositing a perovskite metal oxide thin film on the first metal layer; depositing a second metal layer on the perovskite metal oxide, wherein the metal of the second metal layer is taken from the group of metals consisting of platinum and iridium; annealing the structure at a temperature of between about 400° C. to 700° C. for between about five minutes and three hours; and completing the variable resistance device.

Abstract: An MOCVD process is provided for forming metal-containing films having the general formula M′xM″(1−x)MyOz, wherein M′ is a metal selected from the group consisting of La, Ce, Pr, Nd, Pm, Sm, Y, Sc, Yb, Lu, and Gd; M″ is a metal selected from the group consisting of Mg, Ca, Sr, Ba, Pb, Zn, and Cd; M is a metal selected from the group consisting of Mn, Ce, V, Fe, Co, Nb, Ta, Cr, Mo, W, Zr, Hf and Ni; x has a value from 0 to 1; y has a value of 0, 1 or 2; and z has an integer value of 1 through 7. The MOCVD process uses precursors selected from alkoxide precursors, &bgr;-diketonate precursors, and metal carbonyl precursors in combination to produce metal-containing films, including resistive memory materials.

Abstract: Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes.