Abstract: A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.

Abstract: A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

Abstract: Some implementations described herein provide techniques and apparatuses for overcoming forces that may deflect an injector nozzle into an interior wall of a thin-film furnace. The implementations include a fixture that is coupled to the injector nozzle. The fixture is configurable to lock to a selected property of the injector nozzle to maintain, between a portion of the injector nozzle and the interior wall, a gap. In this way, the portion of the injector nozzle is prevented from colliding with the interior wall and dislodging particulates that may contaminate semiconductor product fabricated using the thin-film furnace.

Abstract: A bonded structure and the method of forming the same are provided. The bonded structure includes a first wafer and a second wafer. The first wafer has a first bonding surface and a plurality of first bonding pads exposed from the first bonding surface. The second wafer has a second bonding surface and a plurality of second bonding pads exposed from the second bonding surface. The first bonding surface faces and contacts the second bonding surface, and the first bonding pads are in contact with and electrically connected to the second bonding pads. Each first bonding pad has a circular shape, and each second bonding pad has an oval shape.

Abstract: Some implementations described herein provide techniques and apparatuses for overcoming forces that may deflect an end portion of an injector nozzle into an interior wall of a thin-film furnace. The implementations include a fixture that is coupled to the end portion of the injector nozzle. The fixture is configurable to lock to a selected property of the end portion to maintain, between the end portion and the interior wall, a gap. In this way, the end portion is prevented from colliding with the interior wall and dislodging particulates that may contaminate semiconductor product fabricated using the thin-film furnace.

Abstract: A semiconductor device including a first semiconductor die, a second semiconductor die, thermal silicon substrates and an encapsulation is provided. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The thermal silicon substrates are disposed on the first semiconductor die, wherein the thermal silicon substrates are spaced apart from the second semiconductor die. The encapsulation is disposed on the first semiconductor die. The encapsulation encapsulates the second semiconductor die and the thermal silicon substrates. The encapsulation includes a filling material layer and an insulator, wherein the filling material layer is disposed on the first semiconductor die and located between the second semiconductor die and thermal silicon substrates, and the filling material layer is spaced apart from the second semiconductor die and the thermal silicon substrates by the insulator.

Abstract: A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, a semiconductor substrate disposed on the dielectric layer and including a via opening with a notch in proximity to the dielectric layer, a through substrate via (TSV) disposed in the via opening of the semiconductor substrate and extending into the dielectric layer to land on the conductive pad, and a dielectric liner disposed in the via opening of the semiconductor substrate and filling the notch to laterally separate the TSV from the semiconductor substrate. A surface of the dielectric liner facing the TSV is substantially leveled with an inner sidewall of the dielectric layer facing the TSV.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor die, a semiconductor frame structure, a semiconductor cover structure and conductive balls. The substrate has a ground plate embedded therein. The semiconductor die is disposed on the substrate and electrically connected with the substrate. The semiconductor frame structure is disposed on the substrate and surrounds the semiconductor die. The semiconductor frame structure includes conductive through semiconductor vias (TSVs) penetrating through the semiconductor frame structure, and at least one conductive TSV is electrically connected with the ground plate. The semiconductor cover structure is disposed on the semiconductor frame structure and on the semiconductor die. The semiconductor cover structure includes a conductive grid pattern and the conductive grid pattern contacts the conductive TSVs.

Abstract: A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, a semiconductor substrate disposed on the dielectric layer and including a via opening with a notch in proximity to the dielectric layer, a through substrate via (TSV) disposed in the via opening of the semiconductor substrate and extending into the dielectric layer to land on the conductive pad, and a dielectric liner disposed in the via opening of the semiconductor substrate and filling the notch to laterally separate the TSV from the semiconductor substrate. A surface of the dielectric liner facing the TSV is substantially leveled with an inner sidewall of the dielectric layer facing the TSV.

Abstract: A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.

Abstract: A semiconductor structure includes a substrate, a bonding structure disposed over the substrate, and a filling layer. The substrate includes an optically active region and an optical surface in the optically active region. The bonding structure includes a bonding dielectric layer and conductive features in the bonding dielectric layer and arranged outside a keep-out zone of the bonding structure, where in a first view, the keep-out zone is located in the optically active region, and a first feature of the conductive features is disposed between the optically active region and the keep-out zone. The filling layer is interposed between the bonding structure and the optically active region of the substrate. The first feature is separated from the filling layer by the bonding dielectric layer in a second view.

Abstract: There is provided an auto detection system including a thermal detection device and a host. The host controls an indication device to indicate a prompt message or detection results according to a slope variation of voltage values or 2D distribution of temperature values detected by the thermal detection device, wherein the voltage values include the detected voltage of a single pixel or the sum of detected voltages of multiple pixels of a thermal sensor.

Abstract: A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.

Abstract: A semiconductor package includes a photonic integrated circuit (PIC) die having a photonic layer, and an electronic integrated circuit (EIC) die bonded to the PIC die. The EIC die includes an optical region that allows the transmission of optical signals through the optical region towards the photonic layer, and a peripheral region outside of the optical region. The optical region includes optical concave/convex structures, a protection film and optically transparent material layers. The optical concave/convex structures are formed in the semiconductor structure. The protection film is conformally disposed over the optical concave/convex structures. The optically transparent material layers are disposed over the protection film and filling up the optical region. The peripheral region includes first bonding pads bonded to the photonic integrated circuit die, and via structures connected to the first bonding pads, wherein the protection film is laterally surrounding sidewalls of the via structures.

Abstract: A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.

Abstract: A system and method for reducing particle contamination on substrates during a deposition process using a particle control system is disclosed here. In one embodiment, a film deposition system includes: a processing chamber sealable to create a pressurized environment and configured to contain a plasma, a target and a substrate in the pressurized environment; and a particle control unit, wherein the particle control unit is configured to provide an external force to each of at least one charged atom and at least one contamination particle in the plasma, wherein the at least one charged atom and the at last one contamination particle are generated by the target when it is in direct contact with the plasma, wherein the external force is configured to direct the at least one charged atom to a top surface of the substrate and to direct the at least one contamination particle away from the top surface of the substrate.

Abstract: There is provided an auto detection system including a thermal detection device and a host. The host controls an indication device to indicate a prompt message or detection results according to a slope variation of voltage values or 2D distribution of temperature values detected by the thermal detection device, wherein the voltage values include the detected voltage of a single pixel or the sum of detected voltages of multiple pixels of a thermal sensor.