Patents by Inventor Wein-Town Sun

Wein-Town Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111273
    Abstract: A method for manufacturing a semiconductor structure includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; removing the silicon nitride layer without removing the first oxide layer; using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and removing the second part of the first oxide layer while remaining the first part of the first oxide layer.
    Type: Application
    Filed: April 21, 2020
    Publication date: April 15, 2021
    Inventors: Wein-Town Sun, Chun-Hsiao Li
  • Patent number: 10892266
    Abstract: A nonvolatile memory structure includes a substrate, a select transistor, and a floating-gate transistor. The substrate includes an oxide defined (OD) region and an erase region. The select transistor is disposed on the OD region, and the floating-gate transistor is disposed on the OD region between the select transistor and the erase region, wherein the floating gate has an extended portion capacitively coupled to the erase region, and the extended portion has an extending direction parallel to a first direction. The OD region further has an addition region protruding in a second direction and partially overlapped with the floating gate, in which the second direction is vertical to the first direction.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: January 12, 2021
    Assignee: eMemory Technology Inc.
    Inventor: Wein-Town Sun
  • Publication number: 20200395081
    Abstract: A memory system includes a non-volatile memory block, a random bit block, and a sense amplifier. The non-volatile memory block includes a plurality of non-volatile memory cells for storing a plurality of bits of data. Each of the non-volatile memory cells includes a first storage transistor. The random bit block includes a plurality of random bit cells for providing a plurality of random bits. Each of the random bit cells includes a second storage transistor and a third storage transistor. The sense amplifier senses a first read current of a non-volatile memory cell during a read operation of the non-volatile memory cell and senses a second read current of a random bit cell during a read operation of the random bit cell. The first storage transistor, the second storage transistor, and the third storage transistor are storage transistors of the same type.
    Type: Application
    Filed: April 14, 2020
    Publication date: December 17, 2020
    Inventor: Wein-Town Sun
  • Publication number: 20200365722
    Abstract: A memory device includes a well, a first gate layer, a second gate layer, a doped region, a blocking layer and an alignment layer. The first gate layer is formed on the well. The second gate layer is formed on the well. The doped region is formed within the well and located between the first gate layer and the second gate layer. The blocking layer is formed to cover the first gate layer, the first doped region and a part of the second gate layer and used to block electrons from excessively escaping. The alignment layer is formed on the blocking layer and above the first gate layer, the doped region and the part of the second gate layer. The alignment layer is thinner than the blocking layer, and the alignment layer is thinner than the first gate layer and the second gate layer.
    Type: Application
    Filed: May 12, 2020
    Publication date: November 19, 2020
    Inventors: Chia-Jung Hsu, Wei-Ren Chen, Wein-Town Sun
  • Publication number: 20200327945
    Abstract: A random bit cell includes a selection transistor, a first P-type transistor, and a second P-type transistor. The selection transistor has a first terminal coupled to a source line, a second terminal coupled to a common node, and a control terminal coupled to a word line. The first P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a first bit line, and a floating gate. The second P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a second bit line, and a floating gate. During an enroll operation, one of the first P-type transistor and the second P-type transistor is programmed by channel hot electron injection.
    Type: Application
    Filed: March 26, 2020
    Publication date: October 15, 2020
    Inventors: Ying-Je Chen, Wein-Town Sun, Wei-Ming Ku
  • Publication number: 20200327946
    Abstract: A random code generator includes a memory cell, two write buffers and two sensing circuits. The memory cell includes a first program path between a first source line and a first bit line, a second program path between the first source line and a second bit line, a first read path between a second source line and a third bit line, and a second read path between a third source line and a fourth bit line. The two write buffers are connected with the first bit line and the second bit line, respectively. The two sensing circuits are connected with the third bit line and the fourth bit line, respectively. The two sensing circuits generate a first output signal and the second output signal to the corresponding write buffers according to the read currents in the corresponding read paths.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 15, 2020
    Inventors: Wei-Ming KU, Wein-Town SUN, Ying-Je CHEN
  • Patent number: 10797063
    Abstract: A single-poly non-volatile memory unit includes: a semiconductor substrate having a first conductivity type; first, second and third OD regions disposed on the semiconductor substrate and separated from each other by an isolation region, wherein the first OD region and the second OD region are formed in a first ion well, and the first ion well has a second conductivity type; a first memory cell disposed on the first OD region, a second memory cell disposed on the second OD region. The first memory cell and the second memory cell exhibit an asymmetric memory cell layout structure with respect to an axis. An erase gate is disposed in the third OD region.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: October 6, 2020
    Assignee: eMemory Technology Inc.
    Inventors: Hsueh-Wei Chen, Wei-Ren Chen, Wein-Town Sun, Jui-Ming Kuo
  • Publication number: 20200294593
    Abstract: An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 17, 2020
    Inventors: Wein-Town SUN, Hsueh-Wei CHEN, Chun-Hsiao LI, Wei-Ren CHEN, Hong-Yi LIAO
  • Publication number: 20200227121
    Abstract: A storage cell includes a selection circuit, a first memory transistor, and a second memory transistor. The selection circuit is coupled to a source line and a common node. When the selection circuit is turned on, the selection circuit forms an electrical connection between the source line and the common node. The first memory transistor has a first terminal coupled to the common node, a second terminal coupled to a first bit line, and a control terminal coupled to a control line. The second memory transistor has a first terminal coupled to the common node, a second terminal coupled to a second bit line, and a control terminal coupled to the control line. The first memory transistor and the second memory transistor are 2-dimension charge-trapping devices or 3-dimension charge-trapping devices.
    Type: Application
    Filed: December 5, 2019
    Publication date: July 16, 2020
    Inventors: Wein-Town Sun, Ching-Hsiang Hsu
  • Publication number: 20200160933
    Abstract: A testing method is provided for testing a memory die of a non-volatile memory. The testing method includes the following steps. Firstly, an erase action is performed on plural memory cells of the memory die. Then, a stress is applied to the plural memory cells of the memory die. Then, a read action is performed on the plural memory cells of the memory die to have the plural memory cells generate plural off currents, and a maximum off current is acquired from the plural off currents. Then, a specified test criterion set is selected from plural test criterion sets according to the maximum off current, and the memory die is tested according to plural test currents or plural test voltages of the specified test criterion set.
    Type: Application
    Filed: September 9, 2019
    Publication date: May 21, 2020
    Inventor: Wein-Town SUN
  • Publication number: 20200006363
    Abstract: An erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. A select gate and a first source/drain terminal of the first select transistor receive a first select gate voltage and a first source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the first floating gate transistor are connected with a second source/drain terminal of the first select transistor and a first bit line voltage, respectively. A select gate and a first source/drain terminal of the second select transistor receive a second select gate voltage and a second source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the second floating gate transistor are connected with the second source/drain terminal of the second select transistor and a second bit line voltage, respectively.
    Type: Application
    Filed: February 21, 2019
    Publication date: January 2, 2020
    Inventors: Chia-Jung HSU, Wein-Town SUN
  • Publication number: 20190214400
    Abstract: A memory structure including a first select transistor, a first floating gate transistor, a second select transistor, a second floating gate transistor, and a seventh doped region is provided. The first select transistor includes a select gate, a first doped region, and a second doped region. The first floating gate transistor includes a floating gate, the second doped region, and a third doped region. The second select transistor includes the select gate, a fourth doped region, and a fifth doped region. The second floating gate transistor includes the floating gate, the fifth doped region, and a sixth doped region. A gate width of the floating gate in the second floating gate transistor is greater than a gate width of the floating gate in the first floating gate transistor. The floating gate covers at least a portion of the seventh doped region.
    Type: Application
    Filed: December 14, 2018
    Publication date: July 11, 2019
    Applicant: eMemory Technology Inc.
    Inventors: Chia-Jung Hsu, Wein-Town Sun
  • Publication number: 20190214401
    Abstract: A single-poly non-volatile memory unit includes: a semiconductor substrate having a first conductivity type; first, second and third OD regions disposed on the semiconductor substrate and separated from each other by an isolation region, wherein the first OD region and the second OD region are formed in a first ion well, and the first ion well has a second conductivity type; a first memory cell disposed on the first OD region, a second memory cell disposed on the second OD region. The first memory cell and the second memory cell exhibit an asymmetric memory cell layout structure with respect to an axis. An erase gate is disposed in the third OD region.
    Type: Application
    Filed: December 25, 2018
    Publication date: July 11, 2019
    Inventors: Hsueh-Wei Chen, Wei-Ren Chen, Wein-Town Sun, Jui-Ming Kuo
  • Patent number: 10262746
    Abstract: A nonvolatile memory structure includes a first PMOS transistor and a first floating-gate transistor on a first active region in a substrate, a second PMOS transistor and a second floating-gate transistor on a second active region in the substrate, and an n-type erase region in the substrate. A source line connects with sources of the first and the second PMOS transistors. A bit line connects with drains of the first and the second floating-gate transistors. A word line connects with first and the second select gates in the first and the second PMOS transistors respectively. An erase line connects with the n-type erase region. The first floating-gate transistor includes a first floating gate with an extended portion extending on a first portion of the n-type erase region. The second floating-gate transistor includes a second floating gate with an extended portion extending on a second portion of the n-type erase region.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: April 16, 2019
    Assignee: eMemory Technology Inc.
    Inventors: Ying-Je Chen, Wei-Ren Chen, Wein-Town Sun
  • Publication number: 20190006378
    Abstract: A nonvolatile memory structure includes a substrate, a select transistor, and a floating-gate transistor. The substrate includes an oxide defined (OD) region and an erase region. The select transistor is disposed on the OD region, and the floating-gate transistor is disposed on the OD region between the select transistor and the erase region, wherein the floating gate has an extended portion capacitively coupled to the erase region, and the extended portion has an extending direction parallel to a first direction. The OD region further has an addition region protruding in a second direction and partially overlapped with the floating gate, in which the second direction is vertical to the first direction.
    Type: Application
    Filed: September 6, 2018
    Publication date: January 3, 2019
    Applicant: eMemory Technology Inc.
    Inventor: Wein-Town Sun
  • Patent number: 10127987
    Abstract: A method for operating a NVM cell is disclosed. The NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor on an N well. The floating gate transistor includes a floating gate and a floating gate extension capacitively coupled to an erase gate region. The method includes erasing the NVM cell by applying an N well voltage VNW to the N well, wherein VNW>0V; applying a source line voltage VSL to a source doping region of the select transistor, wherein VSL=0V; applying a word line voltage VWL to a select gate of the select transistor, wherein VWL=0V; applying a bit line voltage VBL to a drain doping region of the floating gate transistor, wherein VBL=0V; and applying an erase line voltage VEL to the erase gate region, wherein VEL=VEE.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: November 13, 2018
    Assignee: eMemory Technology Inc.
    Inventors: Chia-Jung Hsu, Wein-Town Sun
  • Patent number: 10103157
    Abstract: A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region for forming an erase gate region, and a trench isolation region separating the first OD region from the second OD region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is disposed on the first OD region. The floating gate transistor includes a floating gate overlying the first OD region. A floating gate extension continuously extends from the floating gate to the second OD region. A shallow junction diffusion region is situated directly under the floating gate extension within the second OD region.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 16, 2018
    Assignee: eMemory Technology Inc.
    Inventors: Chun-Hsiao Li, Wei-Ren Chen, Wein-Town Sun
  • Patent number: 10083976
    Abstract: A nonvolatile memory (NVM) cell includes a semiconductor substrate having a first OD region and a second OD region for forming an erase gate (EG) region. The second OD region is spaced apart from the first OD region and is separated from the first OD region by a trench isolation region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is also disposed on the first OD region. The floating gate transistor includes a floating gate overlying the first OD region. A first floating gate extension continuously extends from the floating gate to the second OD region. The first floating gate extension comprises a P+ doped segment and an N+ doped segment with a P+/N+ interface therebetween.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: September 25, 2018
    Assignee: eMemory Technology Inc.
    Inventors: Chia-Jung Hsu, Wein-Town Sun
  • Patent number: 10038003
    Abstract: A single-poly nonvolatile memory cell includes an SOI substrate having a semiconductor layer, a first OD region and a second OD region on the semiconductor layer, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor disposed on the first OD region. The PMOS floating gate transistor is serially connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate overlying the first OD region. A floating gate extension is continuously extended from the floating gate to the second OD region and is capacitively coupled to the second OD region.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: July 31, 2018
    Assignee: eMemory Technology Inc.
    Inventors: Wein-Town Sun, Wei-Ren Chen, Ying-Je Chen
  • Publication number: 20180197875
    Abstract: A nonvolatile memory (NVM) cell includes a semiconductor substrate having a first OD region and a second OD region for forming an erase gate (EG) region. The second OD region is spaced apart from the first OD region and is separated from the first OD region by a trench isolation region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is also disposed on the first OD region. The floating gate transistor includes a floating gate overlying the first OD region. A first floating gate extension continuously extends from the floating gate to the second OD region. The first floating gate extension comprises a P+ doped segment and an N+ doped segment with a P+/N+ interface therebetween.
    Type: Application
    Filed: November 29, 2017
    Publication date: July 12, 2018
    Inventors: Chia-Jung Hsu, Wein-Town Sun