Abstract: A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.

Abstract: Each memory cell of a plurality of memory cells of a memory has a well, source and drain regions, a storage layer, and a gate. The memory cells are in a matrix. Same column drain regions connect to the same bit line, same row gates connect to the same word line, and same column source regions connect to the same source line. The memory is programmed by applying a first voltage to a word line electrically connected to a memory cell of the plurality of memory cells, applying a second voltage different from the first voltage by at least a programming threshold to a bit line electrically connected to the memory cell, applying a third voltage different from the first voltage by at least the programming threshold to a source line electrically connected to the memory cell, and applying a substrate voltage to the plurality of memory cells.

Abstract: By adjusting an operating voltage of a memory cell in a memory according to a measured capacitance result indicating capacitance of an under-test capacitor of the memory cell, an appropriate operating voltage for the memory cell can always be determined according to the measured capacitance result. The measured capacitance result indicates whether the capacitance of the under-test capacitor indicating the characteristic of the gate dielectric of the memory cell is higher or lower than a reference capacitor, and is generated by amplifying a difference between two voltages indicating capacitance of the reference capacitor and the capacitance of the under-test capacitor.

Abstract: A flash memory and a memory cell programming method thereof are provided. The programming method includes the following steps. A preset programming voltage is applied to a memory cell to program the memory cell. A first verify voltage is applied to the memory cell to detect a programming result of the memory cell. A programming voltage applied on the memory cell is adjusted according to the programming result of the memory cell.

Abstract: A nonvolatile memory device for reducing programming current and improving reliability comprises a memory cell array, a write circuit, and a verification circuit. The memory cell array comprises memory cells arranged at crossing points of a bit-line and word-line matrix of the memory cell array. The write circuit provides multiple variable pulses to each word-line for programming. The multiple variable pulses have predetermined amplitude for keeping gate injection current roughly maximum while lowering conduction current during programming operation. The verification circuit senses variation of the conduction current during the programming operation, and disables the programming operation if the sensed conduction current during the programming operation reaches a predetermined value.

Abstract: A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a shaped of L- or of snake from top-view, having a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the poly-Si layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the poly-Si layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line through a source contact.

Abstract: A method of compensating for luminance of an organic light emitting diode is provided. In an embodiment, an operational current of a dummy organic light emitting diode of a color is utilized to simulate the condition that a real pixel current attenuates with time, and a feedback current is outputted accordingly. A compensating voltage is generated according to the feedback current, and is used to regulates the data current inputted to the real pixel so as to compensate for the luminance of the real pixel of the color.

Abstract: A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a shaped of L- or of snake from top-view, having a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the poly-Si layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the poly-Si layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line through a source contact.

Abstract: A method is provided for forming a pixel of an electroluminescence device. The method provides a substrate; defines at least a first area for capacitors, a second area for a transistor on the substrate and a third area for an organic light-emitting diode (OLED) on the substrate; forms first conductive, first dielectric, second conductive, second dielectric, and third conductive layers over the first area; forming a third conductive layer over the second dielectric layer over the first area; wherein the first conductive layer over the first area is directly connected to a power supply voltage, wherein the second conductive layer is electrically connected to a fourth conductive layer and wherein the first conductive layer, the first dielectric layer, and the second conductive layer over the first area collectively form a first one of the capacitors over the first area, the second conductive layer, the second dielectric layer.

Abstract: A method for forming a pixel of an electroluminescence device includes providing a substrate; defining at least a first area for capacitors and a second area for a transistor on the substrate; forming a first conductive layer over the first area; forming a first dielectric layer over the first conductive layer; forming a second conductive layer over the first dielectric layer; forming a second dielectric layer over the second conductive layer; forming a third conductive layer over the second dielectric layer; forming a layer of capping silicon nitride between the second dielectric layer and the third conductive layer; forming a semiconductor layer over the second area; forming a gate oxide layer over the second area; and forming a fourth conductive layer over the gate oxide layer.

Abstract: A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.

Abstract: A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

Abstract: A nonvolatile memory device for reducing programming current and improving reliability comprises a memory cell array, a write circuit, and a verification circuit. The memory cell array comprises memory cells arranged at crossing points of a bit-line and word-line matrix of the memory cell array. The write circuit provides multiple variable pulses to each word-line for programming. The multiple variable pulses have predetermined amplitude for keeping gate injection current roughly maximum while lowering conduction current during programming operation. The verification circuit senses variation of the conduction current during the programming operation, and disables the programming operation if the sensed conduction current during the programming operation reaches a predetermined value.

Abstract: A pixel structure includes a light-emitting device (LED); a first scan line; a data line; a first transistor having a gate coupled to the first scan line; and a current mirror electrically connected to the LED. The current mirror includes a second transistor having a gate connected to the data line and one of the source and the drain of the first transistor, and one of a source and a drain coupled to a first voltage source; and a third transistor having a gate coupled to the other of the source and the drain of the first transistor, one of a source and a drain coupled the first voltage source. The LED is coupled between the other of the source and the drain of the third transistor and a second voltage source whose voltage level is greater than a voltage level of the first voltage source.

Abstract: For providing a compact high-precision lighting control means to drive an LED lighting module, a lighting control integrated circuit is set forth to perform an accurate lighting control. At least one nonvolatile memory is embedded in the lighting control integrated circuit for storing a plurality of lookup tables. One lookup table provides related data for setting the driving currents of the LED lighting module based on spacing or pitch of LED disposition of the LED lighting module. Another lookup table provides related data to recover uniformity for different LED damage situations of the LED lighting module. The other lookup tables are applied to perform compensation processes on the driving currents concerning temperature variation, ambient light intensity, aging degradation, and power-on time. In addition, a signal processing unit, a pulse-width-modulation signal generating module, and a driving module are incorporated in the lighting control integrated circuit for signal processing and current driving.

Abstract: A method for forming a pixel of an electroluminescence device includes providing a substrate; defining at least a first area for capacitors and a second area for a transistor on the substrate; forming a first conductive layer over the first area; forming a first dielectric layer over the first conductive layer; forming a second conductive layer over the first dielectric layer; forming a second dielectric layer over the second conductive layer; forming a third conductive layer over the second dielectric layer; forming a layer of capping silicon nitride between the second dielectric layer and the third conductive layer; forming a semiconductor layer over the second area; forming a gate oxide layer over the second area; and forming a fourth conductive layer over the gate oxide layer.

Abstract: A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

Abstract: An electroluminescence (EL) device includes a substrate and a plurality of pixels formed on the substrate. Each pixel includes a first area including at least a first capacitor and a second capacitor, the first capacitor including a first conductive layer, a first dielectric layer over the first conductive layer, and a second conductive layer over the first dielectric layer, and the second capacitor including the second conductive layer, a second dielectric layer over the second conductive layer, and a third conductive layer over the second dielectric layer, and a second area including a first semiconductor layer formed on the substrate, a first gate oxide layer over the first semiconductor layer, and a fourth conductive layer over the first gate oxide layer.

Abstract: A pixel structure includes a light-emitting device (LED); a first scan line; a data line; a first transistor having a gate coupled to the first scan line; and a current mirror electrically connected to the LED. The current mirror includes a second transistor having a gate connected to the data line and one of the source and the drain of the first transistor, and one of a source and a drain coupled to a first voltage source; and a third transistor having a gate coupled to the other of the source and the drain of the first transistor, one of a source and a drain coupled the first voltage source. The LED is coupled between the other of the source and the drain of the third transistor and a second voltage source whose voltage level is greater than a voltage level of the first voltage source.

Abstract: A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.