Abstract: A timing controller in an LCD has an OTP memory—a one time programmable nonvolatile memory or a MTP memory—a multiple time programmable nonvolatile memory embedded in for storing lookup tables of overdrive functions, dynamic contrast adjustments, independent RGB Gamma curve corrections, and data conversion of cyclic DAC functions. The logic process of the OTP memory and the logic process of the timing controller are completely compatible, and the logic process of the MTP memory only needs two or three photomask processes more than the logic process of the timing controller.

Abstract: An analog-to-digital converter (ADC) for converting an optical signal into an electrical signal is disclosed. The ADC includes a detection module, a first P-type metal oxide semiconductor (PMOS) transistor, a first N-type metal oxide semiconductor (NMOS) transistor, a first switch unit, and an output module. The first PMOS transistor and the first NMOS transistor form an inverter. The first switch unit is disposed between the input terminal and the output terminal of the inverter and is turned on/off according to a first control signal. The output module is coupled to the output terminal of the inverter for counting the time that an input voltage is greater than a reference voltage and generating a digital signal.

Abstract: A negative voltage converter includes six transistors. A first end and a control end of a first transistor are coupled to a signal input. A first end of a second transistor is coupled to the signal input, and a control end of which is coupled to a first clock and the first transistor. A first end of a third transistor is coupled to the signal input, a control end of the third transistor is coupled with a second clock and the second transistor. A first end of a fourth transistor is coupled to the second end of the third transistor, a control end of which is coupled with the first clock and the third transistor. A first end of a fifth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the second clock and the fourth transistor A first end of a sixth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the first clock and the fifth transistor.

Abstract: An electrostatic discharge protection device, an electrostatic discharge protection structure, and a manufacturing process of the device are provided. The electrostatic discharge protection device includes at least four doping regions, wherein two adjacent regions are of different types. The electrostatic discharge protection structure includes an electrostatic discharge bus, a plurality of first electrostatic discharge protection devices connecting to the gates of the display transistors and the electrostatic discharge bus, a plurality of second electrostatic discharge protection devices connecting to the source/drain of the transistors and the electrostatic discharge bus, and a plurality of third electrostatic discharge protection devices connecting to the input/output terminals of the drive circuit of the display and the electrostatic discharge bus.

Abstract: A transistor level shifter circuit constituted by a plurality of PMOS TFT is included. The transistor level shifter circuit primarily includes a conversion circuit, a first amplifier circuit, and a second amplifier circuit. With the simplified circuit arrangement and a smaller quantity of required transistors, the transistor level shifter circuit is adapted to operate efficiency under both high RC load and frequency.

Abstract: A electro-luminescent (EL) display panel includes a substrate, a pixel and a Digital-Analogy Converter (DAC). The substrate includes a first area and a second area. A Thin Film Transistor (TFT) formed in the first area has a first channel doping concentration, and a TFT formed in the second area has a second channel doping concentration. The pixel is disposed in the second area. The DAC includes switch circuits and current sources. Each switch circuit disposed in the second area is selectively turned on according to corresponding grey levels. Each current source disposed in the first area is electrically connected to the corresponding switch circuit and selectively supplying current to generate a pixel current according to conducting states of the corresponding switch circuit. A threshold voltage variation of the TFT formed in the first area is less than that of the TFT formed in the second area.

Abstract: An analog buffer used in a source driver is provided. The analog buffer havs an input end, an output end, a transistor, first and second capacitors, first, second, third, fourth and fifth switches. The source and the drain of the transistor is coupled to the output end and receives a first voltage respectively. The first end of the first and the second capacitors are coupled to the gate of the transistor. The second end of the first and the second capacitors are coupled to the first end of the first, second and fourth switches and the first end of the third and fifth switches respectively. The second end of the first switch receives a second voltage. The second end of the second and third switches are coupled to the input end. The second end of the fourth and fifth switches are coupled to the output end.

Abstract: A pixel device of an electroluminescence device that comprises a voltage signal having a first state and a second state, a current signal, a first circuit further comprising a first transistor, a second transistor and a capacitor, the capacitor including a first terminal coupled to a power supply, the first transistor including a gate electrode coupled to a second terminal of the capacitor, and the second transistor including a gate electrode receiving the voltage signal, wherein the first circuit provides a voltage level across the capacitor in response to the first state of the voltage signal, and maintains the voltage level in response to the second state of the voltage signal, and a second circuit further comprising a third transistor and a fourth transistor, the third transistor including a gate electrode coupled to a gate electrode of the fourth transistor, wherein the second circuit provides a current proportional to the magnitude of the current signal in response to the first state of the voltage sign

Abstract: The present invention provides a circuit for driving a flat panel display, including a storage capacitor, a transmission gate and a current-limiting transistor. A first terminal of the storage capacitor is coupled to a system voltage, and a second terminal of the storage capacitor is at storage voltage. A first input/output terminal of the transmission gate is coupled to the storage voltage, and the second input/output terminal of the transmission gate is coupled to the data current source. A first gate terminal of the transmission gate is coupled to the first signal; a second gate terminal of the transmission gate is coupled to the second signal. A gate terminal of the current-limiting transistor is coupled to the storage voltage, wherein a first source/drain terminal is coupled to the system voltage, and a second source/drain terminal provides current for driving the flat panel display.

Abstract: A data driver for organic light emitting diode display is disclosed. A pixel data of K bits is divided into an N bits data and an M bits data. A number of N bits data are processed by a number of main digital-to-analog current converters and a number of main voltage storing current copier/current mirror so as to generate a number of main regenerating currents. Besides, a number of M bits data are processed by a number of secondary digital-to-analog current converters and a number of secondary voltage storing current copier/current mirror so as to generate a number of secondary regenerating currents. The brightness of the pixel is related to the sum of the corresponding main regenerating current and the corresponding secondary regenerating current. The invention can reduce the error resulted from the component variation of digital-to-analog converters.

Abstract: A display apparatus includes a light-emitting device, a first scan line for transferring a first signal to select the light-emitting device, a data line for transferring a data current signal to drive the light-emitting device, a first transistor having a gate coupled to the first scan line for selecting the light-emitting device according to the first signal, and a current mirror electrically connected to the light-emitting device for transferring a driving current signal to drive the light-emitting device. The current mirror includes a second transistor having a gate coupled to the data line and one of the source and the drain of the first transistor for receiving the data current signal. In addition, the current mirror further includes a third transistor having a gate coupled to the other of the source and the drain of the first transistor for transferring the driving current signal.

Abstract: A transistor level shifter circuit constituted by a plurality of PMOS TFT is disclosed. The transistor level shifter circuit primarily comprises a conversion circuit, a first amplifier circuit, and a second amplifier circuit. With the simplified circuit arrangement and a smaller quantity of required transistors, the transistor level shifter circuit is adapted to operate efficiency under both high RC load and frequency.

Abstract: A structure and a method for reducing source line resistance of a light emitting diode. A light emitting diode display has at least a light emitting diode, a power source and a power source line structure for guiding the power source to provide the required power for driving the light emitting diode. The structure for reducing the source line resistance has an insulation layer formed on at least a part of the source line structure. The insulation layer has at least two openings exposing the source line structure. A conductive layer is formed to cover the insulation layer and is in electrical contact with the source line structure through the openings. Thereby, the conductive layer and the source line are connected in parallel, and the resistance of the source line is thus reduced.

Abstract: An electroluminescence (EL) device includes a substrate and a plurality of pixels formed on the substrate. Each pixel includes a first area including at least a first capacitor and a second capacitor, the first capacitor including a first conductive layer, a first dielectric layer over the first conductive layer, and a second conductive layer over the first dielectric layer, and the second capacitor including the second conductive layer, a second dielectric layer over the second conductive layer, and a third conductive layer over the second dielectric layer, and a second area including a first semiconductor layer formed on the substrate, a first gate oxide layer over the first semiconductor layer, and a fourth conductive layer over the first gate oxide layer.

Abstract: A pixel structure is disclosed. The pixel structure has a light-emitting device; a first scan line for transferring a first signal; a data line for transferring a data current signal; a first transistor having a gate coupled to the first scan line; a current mirror electrically connected to the light-emitting device; and a capacitor. The current mirror includes a second transistor having a gate connected to the data line and one of the source and the drain of the first transistor; and a third transistor having a gate coupled to the other of the source and the drain of the first transistor. The capacitor has two ends coupled to the gate of the third transistor and the light-emitting device respectively, where the capacitor is not coupled to the light-emitting device through the third transistor.

Abstract: A liquid crystal display and its driving method are disclosed. Among the pixels driven by the same data driving unit, firstly the pixels of same color are sequentially driven, and then the pixels of other colors are sequentially driven, so that the pixels have almost the same leakage current.

Abstract: A pixel array of electroluminescence display including a number of data lines, a scan line, and a number of pixels is provided. The pixels are respectively electrically connected to the scan line and the corresponding data lines. Each pixel respectively has a storage capacitor. The storage capacitors have different capacitance values.

Abstract: A display panel for OLED device having a display mode and an input mode. The display panel comprises a driving unit, a capacitor, a light-emitting diode, a light-detecting unit, and a detecting unit. The driving unit has a control electrode coupled to a first node, a first electrode coupled to a first voltage source, and a second electrode. The capacitor and the light-detecting unit are coupled between the first node and the first voltage source. The light-emitting diode is coupled between the control electrode of the driving unit and a second voltage source. In the input mode, the detecting unit detects a voltage at the first node.

Abstract: A time division driven display and a method for driving the same. The display includes a panel having data lines, a source driver having output pins, a precharge controller and a demultiplexer. The precharge controller electrically connected to these data lines selects one from these data lines to precharge. The demultiplexer coupled to the output pins and these data lines couples the corresponding output pin to the selected data line for the source driver to drive the selected data line after the selected data line is precharged.

Abstract: A power-saving circuit for an active matrix liquid crystal display (“LCD”) panel that comprises a plurality of first capacitors, each first capacitor corresponding to a data line of the LCD panel for collecting electrical charge provided on an associated data line, at least one set of second capacitors, at least one set of transistors, each transistor of a set corresponding to one of the plurality of first capacitors, and at least two control signals, each control signal corresponding to a set of the at least one set of transistors and corresponding to a set of the at least one set of second capacitors, and each control signal functioning to switch between a first and a second state to control the operation state of an associated set of transistors, wherein the at least two control signals switch to a first state in a first sequence starting from a first control signal to a last control signal, and then in a second sequence starting from the last control signal to the first control signal, the first sequence