Patents by Inventor Wei-Ting Chen

Wei-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260319728
    Abstract: An interconnectable stereoscopic image interaction system and a method thereof are disclosed. In the system, a sensor of a handheld box-type stereoscopic display device senses an identification component to obtain an object identifier; the handheld box-type stereoscopic display devices are connected to each other through transmission components thereof to exchange the sensed object identifiers; each handheld box-type stereoscopic display device uses the object identifier of another handheld box-type stereoscopic display device as a target identifier, loads a primary image and a secondary image based on the object identifier thereof and the received target identifier to generate virtual stereoscopic images with a primary-secondary relationship for display, thereby achieving the technical effect of enhancing the diversity and interactivity of virtual stereoscopic image.
    Type: Application
    Filed: July 4, 2025
    Publication date: October 15, 2026
    Inventor: Wei-Ting CHEN
  • Publication number: 20260322985
    Abstract: A system of converting a 2D image to a multi-view image for stereoscopic display and a method thereof are disclosed. In the system, the cloud server controls the client to upload a target image, which is 2D, the file conversion server performs image enhancement computation on an initial depth map of the target image to generate a depth-enhanced image, and generate a multi-view image matching a grating film property of a stereoscopic display device based on the depth-enhanced image, the stereoscopic display device displays the multi-view image, superimposes gratings with the multi-view image to present the display images of the multi-view image by viewing angles, respectively, to generate a stereoscopic image through optical principles, thereby preventing malicious use of an image conversion service, and achieving the technical effect of providing different conversion processing efficiencies with different payment plans.
    Type: Application
    Filed: July 7, 2025
    Publication date: October 15, 2026
    Inventor: Wei-Ting CHEN
  • Publication number: 20260322984
    Abstract: A system of converting a 2D image to a 3D image for stereoscopic display and a method thereof are disclosed. In the system, a file conversion server performs an image enhancement computation on a depth map of a 2D target image to generate a depth-enhanced image, and generates a multi-view image matching a grating film property of a stereoscopic display device based on the depth-enhanced image, the stereoscopic display device downloads and displays the multi-view image, so that the stereoscopic display device can superimpose a grating with the multi-view image, display the display images in the multi-view image at different viewing angles to generate the stereoscopic image through an optical principle, thereby improving the display quality of the stereoscopic image and achieving the technical effect of displaying the stereoscopic image with high comfort and high resolution.
    Type: Application
    Filed: July 6, 2025
    Publication date: October 15, 2026
    Inventor: Wei-Ting CHEN
  • Publication number: 20260322993
    Abstract: A handheld box-type stereoscopic display device with integrated embedded space is provided. The handheld box-type stereoscopic display device includes an integrally formed embedded glass trough with rounded edges and corners, an outer surface of the embedded glass trough is opaque, the embedded glass trough is embedded and fixed in an outer shell, the front cover is embedded and fixed with a transparent touch panel, the front cover covers and is fixed in the outer shell to form a seal, and the transparent touch panel covers the embedded glass trough to form a sealed stereoscopic image displayer space for displaying the stereoscopic image, the transparent touch panel realizes touch tapping and sliding operation, thereby achieving the technical effect of providing an integrated embedded space to display the stereoscopic image.
    Type: Application
    Filed: July 6, 2025
    Publication date: October 15, 2026
    Inventor: Wei-Ting CHEN
  • Patent number: 12765374
    Abstract: A semiconductor package with a heat dissipation interface has a substrate, at least one die embedded in the substrate, an insulation layer encompassing the die and covering the substrate, an upper redistribution layer (RDL) and a lower RDL respectively formed on opposite sides of the substrate, wherein an insulated adhesive comprehensively covers the lower RDL, and a dissipation layer is further bonded on the insulated adhesive. The dissipation layer evenly dissipates excessive heat energy generated by the die, thereby improving the heat dissipation efficiency.
    Type: Grant
    Filed: May 3, 2024
    Date of Patent: October 13, 2026
    Assignee: PANJIT INTERNATIONAL INC.
    Inventors: Chung-Hsiung Ho, Chien-Chun Wang, Wei-Ting Chen, Wei-Ting Chen
  • Publication number: 20260313919
    Abstract: A package structure is provided. The package structure includes a first chip structure and a second chip structure over the first chip structure. The first chip structure has a first metal bonding structure, a first conductive via below the first metal bonding structure, and a first dielectric layer laterally surrounding the first metal bonding structure and the first conductive via. The first metal bonding structure is embedded in the first dielectric layer. The package structure also includes a capacitor element positioned between the first metal bonding structure and a bottom surface of the first conductive via. The package structure further includes a second conductive via penetrating through a capacitor dielectric layer of the capacitor element. The second conductive via is electrically isolated from capacitor electrodes of the capacitor element.
    Type: Application
    Filed: June 17, 2026
    Publication date: October 8, 2026
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Ting CHEN, Chung-Hao TSAI, Chen-Hua YU, Chuei-Tang WANG
  • Patent number: 12756810
    Abstract: A system of converting a 2D image to a multi-view image for stereoscopic display and a method thereof are disclosed. In the system, the cloud server controls the client to upload a target image, which is 2D, the file conversion server performs image enhancement computation on an initial depth map of the target image to generate a depth-enhanced image, and generate a multi-view image matching a grating film property of a stereoscopic display device based on the depth-enhanced image, the stereoscopic display device displays the multi-view image, superimposes gratings with the multi-view image to present the display images of the multi-view image by viewing angles, respectively, to generate a stereoscopic image through optical principles, thereby preventing malicious use of an image conversion service, and achieving the technical effect of providing different conversion processing efficiencies with different payment plans.
    Type: Grant
    Filed: July 7, 2025
    Date of Patent: October 6, 2026
    Assignee: LIGHT MATRIX INC.
    Inventor: Wei-Ting Chen
  • Patent number: 12740808
    Abstract: A consumable component of an injecting physiological monitor includes a housing, an injecting module, a physiological monitor, and a carrier. The injecting module is movably assembled on the housing. The physiological monitor is disposed in the housing and located on a movement path of the injecting module. A part of a structure of the physiological monitor is accommodated in a part of a structure of the injecting module. The carrier is disposed in the housing and located on a movement path of the injecting module and the physiological monitor. The carrier and the physiological monitor are separated from each other and located on opposite sides of the housing. The housing and the injecting module are adapted to be assembled to an injector. The injector is adapted to drive the physiological monitor to be assembled to the carrier through the injecting module.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: September 22, 2026
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Ting Chen, Tzu-Chien Lai, I-Hsuan Tsai, Chien Chiu
  • Patent number: 12739353
    Abstract: A stereoscopic image display system based on operations of physical objects and a method thereof are disclosed.
    Type: Grant
    Filed: July 4, 2025
    Date of Patent: September 15, 2026
    Assignee: LIGHT MATRIX INC.
    Inventor: Wei-Ting Chen
  • Publication number: 20260267064
    Abstract: A quantum memory device includes: a waveguide configured to spatially confine paths of photons therein; a memory cell that includes a micro-ring resonator (MRR), a frequency tuner, and a quantum memory material portion, wherein the MRR includes a first segment that is parallel to a segment of the waveguide, wherein the frequency tuner is configured to modulate a photon resonance frequency in the MRR by modifying an effective refractive index within, or around, a second segment of the MRR, and wherein the quantum memory material portion includes a quantum memory material having a ground state and an excitation state that stores photons therein and located within or on a third segment of the MRR; and a control circuit configured to modulate the photon resonance wavelength in the MRR during a first step of a photon capture operation to match a predefined wavelength, and to generate captured photons in the MRR.
    Type: Application
    Filed: April 20, 2026
    Publication date: September 10, 2026
    Inventors: Chung-Hao Tsai, Ching-Ho Chin, Wei-Ting Chen, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 12713628
    Abstract: A package structure and a formation method are provided. The method includes forming a capacitor element over a first chip structure and forming a dielectric layer over the capacitor element. The method also includes forming a conductive bonding structure in the dielectric layer. A top surface of the conductive bonding structure is substantially coplanar with a top surface of the dielectric layer. The conductive bonding structure penetrates through the capacitor element and is electrically connected to the capacitor element. The method further includes bonding a second chip structure to the dielectric layer and the conductive bonding structure through dielectric-to-dielectric bonding and metal-to-metal bonding.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: August 18, 2026
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Ting Chen, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 12701979
    Abstract: A method for forming an interconnection structure includes depositing a dielectric layer over a first interconnect layer, wherein the first interconnect layer comprises a first metallization layer; forming a via opening in the dielectric layer, and forming a conductive via in the via opening. Forming the via opening includes: etching a recess in the dielectric layer above the first metallization layer; etching a first lateral recess in the dielectric layer at a sidewall of the recess; and after etching the first lateral recess, etching the recess downward to expose the first metallization layer.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: August 4, 2026
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Feng Lee, Wei-Ting Chen, Chen-Chung Lai
  • Patent number: 12671418
    Abstract: A signal generator circuit is provided. The gate of a first transistor and the drain of a second transistor are coupled to a first output terminal. The sources of the first and second transistors are coupled to a first power terminal. The drains of the first and third transistors, and the gate of the second transistor are coupled to a second output terminal. The gate of the third transistor is coupled to a second power terminal. The source of the third transistor is coupled to a third power terminal. A fourth transistor is coupled to the second power terminal and the first output terminal. When the third transistor is turned off, a first bias circuit turns on the fourth transistor. A second bias circuit provides a first predetermined voltage to the second transistor. A third bias circuit provides a second predetermined voltage to the first transistor.
    Type: Grant
    Filed: October 2, 2024
    Date of Patent: June 30, 2026
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jung-Tsun Chuang, Chieh-Yao Chuang, Wei-Ting Chen
  • Patent number: 12659036
    Abstract: Systems, devices, and techniques for performing wavelength division multiplexing or demultiplexing using one or more metamaterials in an optical communications systems are described. An optical device may be configured to shift one or more phase profiles of an optical signal using one or more stages of metamaterials to multiplex or demultiplex wavelengths of optical signals. The optical device may be an example of a stacked design with two or more stages of metamaterials stacked on top of one another. The optical device may be an example of a folded design that reflects optical signals between different stages of metamaterials.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: June 16, 2026
    Assignees: CORNING INCORPORATED, HARVARD COLLEGE
    Inventors: Federico Capasso, Wei-Ting Chen, Paulo Clovis Dainese, Jr., Kangmei Li, Ming-Jun Li, Jaewon Oh, Jun Yang
  • Patent number: 12660594
    Abstract: A method for forming a chip package structure is provided. The method includes providing a first substrate and a second substrate. The first substrate includes a first semiconductor base and a first bonding line over a front surface of the first semiconductor base, and the second substrate includes a second semiconductor base and a second bonding line over the second semiconductor base. The method includes bonding the second substrate to the first substrate. The first bonding line is in contact with the second bonding line. The method includes forming a conductive line over a back surface of the first semiconductor base. The conductive line is thicker than the first bonding line. The method includes forming a conductive bump over the back surface of the first semiconductor base. The conductive line is between the conductive bump and the first semiconductor base.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: June 16, 2026
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Wei-Ting Chen, Chia-Chia Lin
  • Publication number: 20260148970
    Abstract: A zinc-vanadium battery includes a modified positive electrode structure (including a positive electrode and a first modified layer), a separator, a negative electrode, and an aqueous electrolyte. The first modified layer on the positive electrode includes 70-95 parts by weight of vanadium-based material, 3-45 parts by weight of a conductive agent, and 3-45 parts by weight of a binder. The negative electrode is on the separator on the first modified layer. The positive electrode, the first modified layer, the separator, and the negative electrode are in the aqueous electrolyte. In the X-ray diffraction patterns of the vanadium-based material measured by XRD using CuK?1 ray, an intensity ratio of a peak at 2?=8°±1.0° over a peak at 2?=20°±1.0° (denoted as I8 and I20, respectively) satisfies 0<I8/I20?1.4. Furthermore, the modified positive electrode structure, a method of manufacturing the modified positive electrode structure, and a method of manufacturing the zinc-vanadium battery are provided.
    Type: Application
    Filed: July 22, 2025
    Publication date: May 28, 2026
    Inventors: Shih Po-Ta Tsai, Wei-Ting Chen, Yi-Hsiu Wang, Chien-Ting Wu
  • Publication number: 20260148975
    Abstract: A zinc-vanadium battery includes a modified positive electrode structure (including a positive electrode and a modified layer), a separator, a negative electrode, and an aqueous electrolyte. The modified layer on the positive electrode includes 70-95 parts by weight of vanadium-based material, 3-45 parts by weight of a conductive agent, and 3-45 parts by weight of a binder. The separator is on the modified layer, and the negative electrode is on the separator. The positive electrode, the modified layer, the separator, and the negative electrode are in the aqueous electrolyte. In the X-ray diffraction patterns of the vanadium-based material measured by XRD using CuK?1 ray, an intensity ratio of a peak at 2?=8°±1.0° over a peak at 2?=20°±1.0° (denoted as I8 and I20, respectively) satisfies 0<I8/I20?1.4. Furthermore, the modified positive electrode structure, a method of manufacturing the modified positive electrode structure, and a method of manufacturing the zinc-vanadium battery are provided.
    Type: Application
    Filed: July 7, 2025
    Publication date: May 28, 2026
    Inventors: Shih Po-Ta Tsai, Wei-Ting Chen, Yi-Hsiu Wang, Chien-Ting Wu
  • Patent number: 12641714
    Abstract: A package capable of eliminating bubble formation includes a composite substrate having an accommodating space, an upper conductive layer and a lower conductive layer; at least one conductive via formed in the composite substrate and electrically connected to the upper conductive layer and the lower conductive layer; a die mounted in the accommodating space and having a first surface and a second surface; a molding layer covering the composite substrate and filled in the at least one conductive via and the accommodating space to wrap the die; the support layer buried in the molding layer and located above the upper conductive layer; a redistribution layer mounted on the molding layer and electrically connected to the first surface of the die and the upper conductive layer; wherein the molding layer is formed by laminating a first insulating sheet and a second insulating sheet.
    Type: Grant
    Filed: December 22, 2023
    Date of Patent: May 26, 2026
    Assignee: PANJIT INTERNATIONAL INC.
    Inventors: Chung-Hsiung Ho, Chi-Hsueh Li, Wei-Ting Chen
  • Patent number: 12631820
    Abstract: A quantum memory device includes: a waveguide configured to spatially confine paths of photons therein; a memory cell that includes a micro-ring resonator (MRR), a frequency tuner, and a quantum memory material portion, wherein the MRR includes a first segment that is parallel to a segment of the waveguide, wherein the frequency tuner is configured to modulate a photon resonance frequency in the MRR by modifying an effective refractive index within, or around, a second segment of the MRR, and wherein the quantum memory material portion includes a quantum memory material having a ground state and an excitation state that stores photons therein and located within or on a third segment of the MRR; and a control circuit configured to modulate the photon resonance wavelength in the MRR during a first step of a photon capture operation to match a predefined wavelength, and to generate captured photons in the MRR.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: May 19, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chung-Hao Tsai, Ching-Ho Chin, Wei-Ting Chen, Chuei-Tang Wang, Chen-Hua Yu
  • Publication number: 20260136660
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.
    Type: Application
    Filed: January 8, 2026
    Publication date: May 14, 2026
    Applicant: Parabellum Strategic Opportunities Fund LLC
    Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Yu-Cheng Liu, Wei-Ting Chen