Patents by Inventor Wen-An Yeh

Wen-An Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11449104
    Abstract: A flexible display that can be adjusted by an electromagnetic mechanism to remove a deformation is disclosed. The flexible display is attached to a body that is configurable in a folded configuration or an unfolded configuration by a hinge mechanism. When unfolded the flexible display includes a deformation (i.e., warp) in an area around the hinge mechanism. Accordingly, an electromagnet is included with the hinge mechanism to remove the deformation by attracting a magnetic element is disposed on a back surface of the flexible display.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: September 20, 2022
    Assignee: Google LLC
    Inventors: Wenli Tan, Victor Cheng, Vincent Chien, Davis Ou, Eugene Liao, Han-Wen Yeh, Mike Liu, Chun Tseng
  • Patent number: 11437745
    Abstract: A card connector includes a transmission conductor assembly. The transmission conductor assembly includes a first conductor group and a second conductor group. The first conductor group includes a backup transmission conductor, first and second signal transmission conductors, an inspection signal transmission conductor, first to seventh grounding transmission conductors, a command reset transmission conductor, first to sixth differential transmission conductors, first and second power transmission conductors, and a write-protection transmission conductor, each of which has two ends respectively forming a spring section and a soldering section. The second conductor group includes eighth to tenth grounding transmission conductors, seventh to tenth differential transmission conductors, and a third power transmission conductor each of which has two ends respectively forming a spring section and a soldering section.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: September 6, 2022
    Assignee: V-GENERAL TECHNOLOGY CO., LTD.
    Inventors: Po-Wen Yeh, Hsuan Ho Chung, Yung-Chang Lin, Yu Hung Lin, Tzu-Wei Yeh, Yu-Lun Yeh
  • Publication number: 20220190716
    Abstract: A transmitter is provided. the transmitter includes a hybrid feedback circuit and a hybrid driving circuit. The hybrid feedback circuit compares a reference voltage with a feedback voltage in closed-loop, determines whether to perform polarity reversal according to a mode control signal, controls power output according to a comparison result and the mode control signal, and generates a first output signal. The hybrid driving circuit, coupled to the hybrid feedback circuit, receives the first output signal of the hybrid feedback circuit, generates a transmitter output signal according to an input data, and generates a second output signal according to the transmitter output signal. The first output signal and the second output signal are transmitted back to the hybrid feedback circuit.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 16, 2022
    Inventors: Chun-Wen YEH, Ching-Lung TI, Chia-Chieh TU
  • Publication number: 20220157605
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Inventors: Shih-Chun HUANG, Chiu-Hsiang CHEN, Ya-Wen YEH, Yu-Tien SHEN, Po-Chin CHANG, Chien-Wen LAI, Wei-Liang LIN, Ya Hui CHANG, Yung-Sung YEN, Li-Te LIN, Pinyen LIN, Ru-Gun LIU, Chin-Hsiang LIN
  • Patent number: 11289332
    Abstract: A method of fabricating a semiconductor device includes forming a hard mask layer over a substrate. A multi-layer resist is formed over the hard mask layer. The multi-layer resist is etched to form a plurality of openings in the multi-layer resist to expose a portion of the hard mask layer. Ion are directionally provided at an angle to the multi-layer resist to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In one embodiment, the multi-layer resist is directionally etched by directing etch ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In another embodiment, the multi-layer resist is directionally implanted by directing implant ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Chin-Hsiang Lin, Chien-Wen Lai, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Yu-Tien Shen, Ya-Wen Yeh
  • Publication number: 20220069211
    Abstract: A pillar-shaped structure and a line-shaped structure are described that include a supporting top conductive layer, an active material layer, such as a memory material or switching material, and a bottom conductive layer. The active material layer is more narrow than the supporting top conductive layer. A supporting side insulating layer is formed connecting the top and bottom conductive layers to provide structure stability. A void, or air gap, is formed between the active material layer and the supporting side insulating layer, which can provide improved thermal isolation between adjacent pillar-shaped or line-shaped structures.
    Type: Application
    Filed: September 3, 2020
    Publication date: March 3, 2022
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hsiang-Lan LUNG, Chiao-Wen YEH
  • Patent number: 11239078
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Chiu-Hsiang Chen, Ya-Wen Yeh, Yu-Tien Shen, Po-Chin Chang, Chien Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Li-Te Lin, Pinyen Lin, Ru-Gun Liu, Chin-Hsiang Lin
  • Publication number: 20210408705
    Abstract: A card connector includes a transmission conductor assembly. The transmission conductor assembly includes a first conductor group and a second conductor group. The first conductor group includes a backup transmission conductor, first and second signal transmission conductors, an inspection signal transmission conductor, first to seventh grounding transmission conductors, a command reset transmission conductor, first to sixth differential transmission conductors, first and second power transmission conductors, and a write-protection transmission conductor, each of which has two ends respectively forming a spring section and a soldering section. The second conductor group includes eighth to tenth grounding transmission conductors, seventh to tenth differential transmission conductors, and a third power transmission conductor each of which has two ends respectively forming a spring section and a soldering section.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 30, 2021
    Inventors: PO-WEN YEH, HSUAN HO CHUNG, YUNG-CHANG LIN, YU HUNG LIN, TZU-WEI YEH, YU-LUN YEH
  • Publication number: 20210399481
    Abstract: A card connector includes a transmission conductor assembly that includes a backup transmission conductor, a first signal transmission conductor, an inspection signal transmission conductor, a first grounding transmission conductor, a command reset transmission conductor, a first differential transmission conductor, a second differential transmission conductor, a second grounding transmission conductor, a third grounding transmission conductor, a fourth grounding transmission conductor, a first power transmission conductor, a second power transmission conductor, a third differential transmission conductor, a fourth differential transmission conductor, a second signal transmission conductor, a fifth grounding transmission conductor, a sixth grounding transmission conductor, a seventh grounding transmission conductor, a fifth differential transmission conductor, a sixth differential transmission conductor, and a write-protection transmission conductor, each of which has two ends respectively forming a spring se
    Type: Application
    Filed: June 16, 2021
    Publication date: December 23, 2021
    Inventors: PO-WEN YEH, HSUAN HO CHUNG, YUNG-CHANG LIN, YU HUNG LIN, TZU-WEI YEH, YU-LUN YEH
  • Publication number: 20210399482
    Abstract: A card connector includes a transmission conductor assembly. The transmission conductor assembly includes a first signal transmission conductor, a first power transmission conductor, an inspection signal transmission conductor, a second signal transmission conductor, a command reset transmission conductor, a first grounding transmission conductor, a second power transmission conductor, a first differential transmission conductor, a second differential transmission conductor, a third signal transmission conductor, a second grounding transmission conductor, a third grounding transmission conductor, a third differential transmission conductor, a fourth differential transmission conductor, a fourth grounding transmission conductor, a fifth grounding transmission conductor, a fifth differential transmission conductor, a sixth differential transmission conductor, and an outside grounding transmission conductor, each of which has a spring section and a soldering section.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 23, 2021
    Inventors: PO-WEN YEH, HSUAN HO CHUNG, YUNG-CHANG LIN, YU HUNG LIN, TZU-WEI YEH, YU-LUN YEH
  • Publication number: 20210375639
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Application
    Filed: August 16, 2021
    Publication date: December 2, 2021
    Inventors: Ya-Wen YEH, Yu-Tien SHEN, Shih-Chun HUANG, Po-Chin CHANG, Wei-Liang LIN, Yung-Sung YEN, Wei-Hao WU, Li-Te LIN, Pinyen LIN, Ru-Gun LIU
  • Publication number: 20210358752
    Abstract: A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 18, 2021
    Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
  • Publication number: 20210272807
    Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Chang, Li-Te Lin, Ru-Gun Liu, Wei-Liang Lin, Pinyen Lin, Yu-Tien Shen, Ya-Wen Yeh
  • Patent number: 11094556
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Wen Yeh, Yu-Tien Shen, Shih-Chun Huang, Po-Chin Chang, Wei-Liang Lin, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Pinyen Lin, Ru-Gun Liu
  • Publication number: 20210240907
    Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.
    Type: Application
    Filed: April 21, 2021
    Publication date: August 5, 2021
    Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien-Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
  • Patent number: 11075079
    Abstract: A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
  • Publication number: 20210204438
    Abstract: A server includes a first server unit, a second server unit, a hinge and a connecting element. The second server unit is disposed on the first server unit and is electrically connected to the first server unit. The second server unit is pivoted to the first server unit through the hinge. The connecting element is disposed between the first server unit and the second server unit. The connecting element has a first connection end and a second connection end, wherein the first connection end is connected to the first server unit, and the second connection end is connected to the second server unit. A server system including a rack and at least one server is also provided.
    Type: Application
    Filed: October 27, 2020
    Publication date: July 1, 2021
    Applicants: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, Lite-On Technology Corporation
    Inventors: Wei-Ming Shieh, Yi-Feng Pu, Chien-Wen Yeh, Hung-Hsing Chiu, Pei-Hsuan Huang
  • Patent number: 11043381
    Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.
    Type: Grant
    Filed: January 27, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Chang, Li-Te Lin, Ru-Gun Liu, Wei-Liang Lin, Pinyen Lin, Yu-Tien Shen, Ya-Wen Yeh
  • Publication number: 20210165457
    Abstract: A flexible display that can be adjusted by an electromagnetic mechanism to remove a deformation is disclosed. The flexible display is attached to a body that is configurable in a folded configuration or an unfolded configuration by a hinge mechanism. When unfolded the flexible display includes a deformation (i.e., warp) in an area around the hinge mechanism. Accordingly, an electromagnet is included with the hinge mechanism to remove the deformation by attracting a magnetic element is disposed on a back surface of the flexible display.
    Type: Application
    Filed: November 5, 2019
    Publication date: June 3, 2021
    Inventors: Wenli Tan, Victor Cheng, Vincent Chien, Davis Ou, Eugene Liao, Han-Wen Yeh, Mike Liu, Chun Tseng
  • Patent number: 10990744
    Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang