Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate and forming a plurality of openings in the patterning layer. The substrate includes a plurality of features to receive a treatment process. The openings partially overlap with the features from a top view while a portion of the features remains covered by the patterning layer. Each of the openings is free of concave corners. The method further includes performing an opening expanding process to enlarge each of the openings and performing a treatment process to the features through the openings. After the opening expanding process, the openings fully overlap with the features from the top view.

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Abstract: An isolated nucleic acid encoding a C-terminal fragment of paraspeckle component 1 (PSPC1) is disclosed. The C-terminal fragment of the PSPC1 comprises an extension of more than 10 but no greater than 131 amino acid residues with its C-terminal amino acid identical to the C-terminus of the PSPC1 sequence SEQ ID NO: 3 and exhibits a biological activity against tumor cells. The tumor cells are associated with either PSPC1 or protein tyrosine kinase 6 (PTK6), or both. The anti-tumor activity is at least one selected from the group consisting of: (a) suppressing tumor cell growth; (b) suppressing tumor cell progression; (c) suppressing tumor cell metastasis; (d) decreasing PSPC1 expression; and (e) decreasing oncogenic PTK6 expression in cytoplasm. Also disclosed is a peptide comprising a C-terminal fragment sequence of PSPC1. A reagent kit and method for predicting tumor progression, metastasis, and prognosis in a cancer patient are also disclosed.

Abstract: A 3D memory includes a plurality of first access line levels, a plurality of second access line levels and a plurality of memory cell levels, the memory cell levels being disposed between corresponding first access line levels and second access line levels. The first access line levels include a plurality of first access lines extending in a first direction, and a plurality of remnants of a first sacrificial material disposed between the first access lines. The second access line levels include a plurality of second access lines extending in a second direction and a plurality of remnants of a second sacrificial material disposed between the second access lines. The memory cell levels include an array of memory pillars disposed in the cross-points between the first access lines and the second access lines in adjacent first and second access line levels.

Abstract: In a general aspect, a foldable display device may include a processor, a memory, a first housing having a first end portion and a second end portion, a first length extending between the first end portion and the second end portion of the first housing, a second housing having a first end portion and a second end portion, a second length extending between the first end portion and the second end portion of the second housing, the second length being different than the first length, a flexible display coupled to the first housing and the second housing, and a hinge assembly coupled to the first housing and the second housing for relative rotation of the first housing and the second housing. The hinge assembly may include a slider, a lever attached to the slider, a set of gears disposed on the slider, and a linkage member connecting the lever and the set of gears together.

Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate, wherein the substrate includes a plurality of features to receive a treatment process; forming at least one opening in the patterning layer, wherein the plurality of features is partially exposed in the at least one opening; applying a directional etching to expand the at least one opening in a first direction, thereby forming at least one expanded opening; and performing the treatment process to the plurality of features through the at least one expanded opening.

Abstract: An integrated circuit includes a three-dimensional cross-point memory having a plurality of levels of memory cells disposed in cross points of first access lines and second access lines with alternating wide and narrow regions. The manufacturing process of the three-dimensional cross-point memory includes patterning with three patterns: a first pattern to define the memory cells, a second pattern to define the first access lines, and a third pattern to define the second access lines.

Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

Abstract: An electronic device includes: a processor; a memory; a first body portion; a second body portion coupled to the first body portion by a hinge, the second body portion including a plate; a slider having a slot therein, wherein the plate slidingly engages with the slot to facilitate the slider assuming at least first and second positions relative to the second body portion; and a flexible display attached to the first body portion and the slider, wherein the flexible display has a substantially planar configuration in the first position of the slider and a substantially folded configuration in the second position of the slider.

Abstract: An electronic device includes: a processor; a memory; a first body member; a second body member; a flexible display, wherein a first portion of the flexible display is mounted to the first body member, and wherein a second portion of the flexible display is mounted to the second body member; a shaft mounted to the second body member; a hinge coupled to the first and second body members; a first arm having a first pivot with the first body member; and a threaded coupling between the first arm and the shaft.

Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.

Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

Abstract: An electronic device includes: a processor; a memory; a first body member; a second body member; a flexible display, wherein a first portion of the flexible display is mounted to the first body member, and wherein a second portion of the flexible display is mounted to the second body member; a shaft mounted to the second body member; a hinge coupled to the first and second body members; a first arm having a first pivot with the first body member; and a threaded coupling between the first arm and the shaft.

Abstract: An electronic device includes: a processor; a memory; a first body portion; a second body portion coupled to the first body portion by a hinge, the second body portion including a plate; a slider having a slot therein, wherein the plate slidingly engages with the slot to facilitate the slider assuming at least first and second positions relative to the second body portion; and a flexible display attached to the first body portion and the slider, wherein the flexible display has a substantially planar configuration in the first position of the slider and a substantially folded configuration in the second position of the slider.

Abstract: In a general aspect, a foldable display device may include a processor, a memory, a first housing having a first end portion and a second end portion, a first length extending between the first end portion and the second end portion of the first housing, a second housing having a first end portion and a second end portion, a second length extending between the first end portion and the second end portion of the second housing, the second length being different than the first length, a flexible display coupled to the first housing and the second housing, and a hinge assembly coupled to the first housing and the second housing for relative rotation of the first housing and the second housing. The hinge assembly may include a slider, a lever attached to the slider, a set of gears disposed on the slider, and a linkage member connecting the lever and the set of gears together.

Abstract: A wavelength conversion film including a phosphor layer and a light scattering layer is provided. The phosphor layer includes a first phosphor and a first substrate. The light scattering layer includes a plurality of titanium dioxide particles and a second substrate. The wavelength conversion film further includes a photoluminescence material and a plurality of nanoparticles. The photoluminescence material and the plurality of nanoparticles are located in at least one of the phosphor layer and the light scattering layer or respectively located in the phosphor layer and the light scattering layer. The wavelength conversion film of the invention may prevent the occurrence of photocatalytic effect and increase the light conversion efficiency.

Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Abstract: The present invention discloses a light emitting element comprising a printed circuit board and a light emitting diode. The printed circuit board comprises a photosensitive solder resist layer. Materials of the photosensitive solder resist layer comprise a reflective material and at least one of a conductive nanoparticle and a photoluminescent material. The light emitting diode is disposed on the photosensitive solder resist layer of the circuit board, and is electrically connected to the printed circuit board. By adding at least one of the conductive nanoparticle and the photoluminescent material, the light emitting element of the present invention reduces the photodegradation of the solder resist layer, and improves the reflectivity of the photosensitive solder resist layer.

Abstract: A 3D memory includes a plurality of first access line levels, a plurality of second access line levels and a plurality of memory cell levels, the memory cell levels being disposed between corresponding first access line levels and second access line levels. The first access line levels include a plurality of first access lines extending in a first direction, and a plurality of remnants of a first sacrificial material disposed between the first access lines. The second access line levels include a plurality of second access lines extending in a second direction and a plurality of remnants of a second sacrificial material disposed between the second access lines. The memory cell levels include an array of memory pillars disposed in the cross-points between the first access lines and the second access lines in adjacent first and second access line levels.

Abstract: An integrated circuit includes a three-dimensional cross-point memory having a plurality of levels of memory cells disposed in cross points of first access lines and second access lines with alternating wide and narrow regions. The manufacturing process of the three-dimensional cross-point memory includes patterning with three patterns: a first pattern to define the memory cells, a second pattern to define the first access lines, and a third pattern to define the second access lines.