Abstract: An illumination module includes a light source configured to emit an illumination light beam, a reflective light valve disposed on a path of the illumination light beam and configured to form a plurality of pixels, a lens, and an image sensing module. Each pixel is adapted to be switched between a first state and a second state. The pixels in the first state among the pixels are configured to reflect the illumination light beam into an effective light beam. The pixels in the second state among the pixels are configured to reflect the illumination light beam into a complementary light beam. The lens is disposed on a path of the effective light beam and configured to project the effective light beam to an area to be illuminated. The image sensing module is disposed on a path of a complementary light beam from the reflective light valve and configured to sense the complementary light beam.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a metallization layer. The metallization layer is disposed over the substrate. The metallization layer includes a first signal line, a second signal line, and a third signal line, wherein the first signal line, the second signal line, and the third signal line are arranged in a first row between a power rail and a ground rail parallel to the power rail. A first distance between the first signal line and the second signal line is different from a second distance between the second signal line and the third signal line. A method for manufacturing a semiconductor structure is also provided.

Abstract: A pixel circuit and a display device are provided. The pixel circuit includes a light-emitting component, a first light sensor, and a variable resistor. The first light sensor receives a first operation voltage, and provides a first control voltage according to an intensity of a first sensed light. The variable resistor adjusts a resistance value provided therefrom according to the first control voltage so as to adjust a current value of a driving current flowing through the light-emitting component.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: An electronic memory device includes a memory-cell circuit. The electronic memory device also includes a non-memory-cell circuit. The non-memory cell circuit includes an active region. The active region extends in a first direction in a top view. The active region includes a first segment and a second segment. The first segment has a first dimension measured in a second direction in the top view. The second segment has a second dimension measured in the second direction different from the first direction in the top view. The second dimension is different from the first dimension.

Abstract: A robust human cell culture model permissive to both SARS-COV-2 variants and MERS-COV is critical for assessment and validation of antivirals. Human alveolar A549 cells are regarded as a valuable model for respiratory virus infection. SARS-COV-2 uses the angiotensin converting enzyme 2 (ACE2) receptor for viral entry and the transmembrane serine protease 2 (TMPRSS2) to prime the SARS-COV-2 spike protein. By contrast, MERS-COV utilizes the dipeptidyl peptidase 4 receptor (DPP4) to enter the target cells. Three of which are negligibly expressed in A549. Disclosed herein is a generation of a robust human cell model that carries DPP4, ACE2, and TMPRSS2 receptor expressions. By transducing Dpp4 into A549-ACE2plusC3 cells (ACE2+/TMPRSS2+), the resulting cells expressing DPP4, ACE2 and TMPRSS2 (“ACE2plusC3D4”) are highly susceptible to MERS-COV and SARS-CoV-2 omicron infection. This ACE2plusC3D4 cell model can be applied for evaluation of antiviral drugs and potentially developed for high-throughput screening.

Abstract: An electrode assembly includes a negative electrode plate, a positive electrode plate, and a separator disposed between the negative electrode plate and the positive electrode plate. The negative electrode plate, the positive electrode plate, and the separator are wound together around a winding axis to form the electrode assembly. The negative electrode plate is a continuous negative electrode plate extending from a foremost winding end to a hindmost winding end along a winding direction. The positive electrode plate includes a continuous positive electrode plate disposed along the winding direction as well as a single-sheet positive electrode plate and/or a long-sheet positive electrode plate disposed along the winding direction apart from the continuous positive electrode plate.

Abstract: A high-speed nail combined with an inner-toothed tube having an expandable padding includes: a main body including a tubular member and an expandable flange, the tubular member including a first space and a threaded portion, the expandable flange integrally projecting form the tubular member and expending in a nailing direction to define a second space, the second space being in communication with the first space; a drive pin connected to the tubular member by insertion in the nailing direction, including a nail head and a nail body connected to each other, the nail head being located in the first space, the nail body extending from the first space to the second space; and a gunpowder actuating unit received in the first space.

Abstract: A semiconductor structure according to the present disclosure includes a first memory array in a first cache and a second memory array in a second cache. The first memory array includes a plurality of first memory cells arranged in M1 rows and N1 columns. The second memory array includes a plurality of second memory cells arranged in M2 rows and N2 columns. The semiconductor structure also includes a first bit line coupled to a number of N1 first memory cells in one of the M1 rows, and a second bit line coupled to a number of N2 second memory cells in one of the M2 rows. N1 is smaller than N2, and a width of the first bit line is smaller than a width of the second bit line.

Abstract: A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin. The first and the second semiconductor fins extend lengthwise along a first direction over a substrate. A metal gate structure is disposed over the first and second semiconductor fins, the metal gate structure extending lengthwise along a second direction perpendicular to the first direction. A first epitaxial source/drain (S/D) feature is disposed over the first semiconductor fin, and a second epitaxial S/D feature is disposed over the second semiconductor fin. An interlayer dielectric (ILD) layer is disposed over the first and the second epitaxial S/D features. And an S/D contact is disposed directly above the first and second epitaxial S/D features. The S/D contact directly contacts the first epitaxial S/D feature, and the S/D contact is isolated from the second epitaxial S/D feature by the ILD layer.

Abstract: A high-speed nail combined with an inner-toothed tube having an expandable padding includes: a main body including a tubular member and an expandable flange, the tubular member including a first space and a threaded portion, the expandable flange integrally projecting form the tubular member and expending in a nailing direction to define a second space, the second space being in communication with the first space; a drive pin connected to the tubular member by insertion in the nailing direction, including a nail head and a nail body connected to each other, the nail head being located in the first space, the nail body extending from the first space to the second space; and a gunpowder actuating unit received in the first space.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip comprising a memory cell. The memory cell is disposed within a dielectric structure that overlies a substrate. The memory cell comprises a data storage structure disposed between a bottom electrode and a top electrode. An upper conductive structure is disposed in the dielectric structure and on the top electrode. The upper conductive structure comprises a protrusion disposed below an upper surface of the top electrode. A sidewall spacer structure is disposed around the memory cell. The sidewall spacer structure comprises a first sidewall spacer layer around the data storage structure and a second sidewall spacer layer abutting the first sidewall spacer layer. The protrusion contacts the second sidewall spacer layer.

Abstract: A computer operating system is provided. The computer operating system includes a control host, a display device, and a mouse. The display device is connected to the control host. The mouse is connected to the control host. The control host is used to generate a first mouse icon on the display device and generate a second mouse icon on the display device when the first mouse icon exists, wherein a pattern of the first mouse icon is different from a pattern of the second mouse icon.

Abstract: A method performed by a UE for Delay Status Reporting (DSR) is provided. The method receives, from a BS, configuration information related to a Logical Channel Group (LCG). The method generates a DSR Medium Access Control (MAC) Control Element (CE) including a first field indicating a buffer size for the LCG and transmits the DSR MAC CE to the BS. The buffer size indicates a total amount of delay-critical data for the LCG. The delay-critical data for the LCG includes a first Packet Data Convergence Protocol (PDCP) Service Data Unit (SDU), for which a first discard timer has a remaining time value less than a time threshold associated with the LCG, and a second PDCP SDU belonging to a Protocol Data Unit (PDU) set that includes at least one PDCP SDU for which a second discard timer has a remaining time value less than the time threshold.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: An optical waveguide element, including a first optical waveguide, a second optical waveguide, a third optical waveguide, and a grating, is provided. The second optical waveguide is disposed on the first optical waveguide. The third optical waveguide is disposed on the second optical waveguide. The grating is disposed between the first optical waveguide and the second optical waveguide. A refractive index of the second optical waveguide is smaller than a refractive index of the first optical waveguide and a refractive index of the third optical waveguide. A head-mounted display is also provided.

Abstract: A light guide substrate, including a light coupling-in region with multiple first gratings, a light expansion region with multiple sub light expansion regions, and a light coupling-out region, is provided. Each sub light expansion region includes multiple second gratings. The sub light expansion regions include a first set of sub light expansion regions and a second set of sub light expansion regions. Each second grating in the first set of sub light expansion regions includes a first microstructure and a second microstructure. The light coupling-out region includes multiple third gratings. When an image light enters the light guide substrate from the light coupling-in region through the first gratings, the image light is first transmitted to the light expansion region in the light guide substrate, then transmitted to the light coupling-out region through the second gratings, and then emitted from the light coupling-out region through the third gratings.

Abstract: A high-speed gunpowder actuated nail with a toothed tube includes: a nail member including an outer threaded portion; a tubular member including an inner threaded portion screwed to the outer threaded portion; an actuating portion mounted to the tubular member; and a percussion cap mounted to an end of the tubular member remote from the nail member. As such, it can be applied for effective screw connection of a threaded rod of small size, and the threaded rod and the nail member are arranged to be perpendicular to each other so that it has high structural strength, which improves the assembly strength to solve the difficulty and high cost of processing the inner thread of the tubular portion of the conventional one-piece high-speed nail, and solve the problem of insufficient screw connection strength due to the insufficient teeth of the conventional hanger.

Abstract: A static random-access memory (SRAM) structure and the manufacturing method thereof are disclosed. An exemplary SRAM structure includes a first source/drain (S/D) feature and a second S/D feature formed in an interlayer dielectric layer (ILD) of a bit cell region of the SRAM structure, a frontside via electrically connecting to the first S/D feature, and a first backside via electrically connecting to the second S/D feature. The first S/D feature and the second S/D feature are of a same type.