Patents by Inventor Wen Chang

Wen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240151900
    Abstract: A method for manufacturing a semiconductor device includes: forming a first waveguide structure and a second waveguide structure on a substrate in which the first waveguide structure and the second waveguide structure is spaced apart from each other by a recess; conformally forming an un-doped dielectric layer to cover the first and second waveguide structures and to form a gap between two corresponding portions of the un-doped dielectric layer laterally covering the first waveguide structure and the second waveguide structure, respectively; and forming a doped filling layer to fill the gap.
    Type: Application
    Filed: February 22, 2023
    Publication date: May 9, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Li LO, Huan-Chieh CHEN, Yao-Wen CHANG, Chih-Ming CHEN
  • Publication number: 20240155758
    Abstract: An electronic device is provided. The electronic device includes a first dielectric layer, an electronic element, an encapsulant, and a second dielectric layer. The first dielectric layer has a first coefficient of thermal expansion (CTE). The electronic element is disposed over the first dielectric layer. The encapsulant encapsulates the electronic element and has a second CTE. The second dielectric layer is disposed over the encapsulant and having a third CTE. The second CTE ranges between the first CTE and the third CTE.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 9, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien Lin CHANG CHIEN, Yuan-Chun TAI, Yu Hsin CHANG CHIEN, Chiu-Wen LEE, Chang Chi LEE
  • Publication number: 20240155185
    Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Inventors: Chia-Hao CHANG, You-Tsai JENG, Kai-Wen YEH, Yi-Cheng CHEN, Te-Chuan WANG, Kai-Wen CHENG, Chin-Lung LIN, Tai-Lai TUNG, Ko-Yin LAI
  • Publication number: 20240154149
    Abstract: An electrode plate stacking method includes: determining, based on a first electrode plate, a conveying order of a plurality of second electrode plates, the first electrode plate being a continuous electrode plate, the plurality of second electrode plates including at least one upper electrode plate and at least one lower electrode plate, the plurality of second electrode plates being discontinuous electrode plates, and the conveying order being used for conveying the at least one upper electrode plate and the at least one lower electrode plate alternately; generating an identifier sequence for the plurality of second electrode plates based on the conveying order; and collecting first image data of each of the plurality of second electrode plates based on the identifier sequence in a process of conveying the plurality of second electrode plates in the conveying order.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Applicant: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Shiping FENG, Jun HU, Canbin CHEN, Wen CHANG, Qiuhui ZHENG, Qing WU, Haoran LU, Jiayi ZHAO, Yitai GUO
  • Patent number: 11978736
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first fin projecting vertically from a semiconductor substrate. A second fin projects vertically from the semiconductor substrate, where the second fin is spaced from the first fin, and where the first fin has a first uppermost surface that is disposed over a second uppermost surface of the second fin. A nanostructure stack is disposed over the second fin and vertically spaced from the second fin, where the nanostructure stack comprises a plurality of vertically stacked semiconductor nanostructures. A pair of first source/drain regions is disposed on the first fin, where the first source/drain regions are disposed on opposite sides of an upper portion of the first fin. A pair of second source/drain regions is disposed on the second fin, where the second source/drain regions are disposed on opposite sides of the nanostructure stack.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Min Cao, Shang-Wen Chang
  • Patent number: 11975329
    Abstract: An incubation system includes an actuator, a platform, an incubation lid, and a dispenser. The actuator includes a motion disc and a shaft connected to the motion disc. The shaft extends away from the motion disc. The platform is connected to the shaft of the actuator in a manner allowing movement transmission. The platform has a through hole and a thermal conductive plate. One end of the through hole is sealed by the thermal conductive plate. The incubation lid is movably disposed over the platform. The platform is thermal insulating. The incubation lid has an opening allowing fluid communication, and the dispenser suspends over the thermal conductive plate of the platform.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: May 7, 2024
    Assignee: LifeOS Genomics Corporation
    Inventors: Timothy Z. Liu, Hung-Wen Chang
  • Publication number: 20240141427
    Abstract: Presented herein are altered polymerase enzymes for improved incorporation of nucleotides and nucleotide analogues, in particular altered polymerases that maintain low error rate, low phasing rate, or increased incorporation rate for a second generation ffN under reduced incorporation times, as well as methods and kits using the same.
    Type: Application
    Filed: September 27, 2023
    Publication date: May 2, 2024
    Applicant: ILLUMINA, INC.
    Inventors: Misha Golynskiy, Rahman Rahman Pour, Jiawen Li, Ryan Craig, Hamed Tabatabaei Ghomi, Saurabh Nirantar, Hsu Myat Noe, Lin Hui Chang, Yvonne Devadas, Jing Wen Lim, Kay Klausing, Humberto Rojo, Eric Murtfeldt, Chris Garcia
  • Publication number: 20240142629
    Abstract: A shielding structure may be applied on an electronic device. The electronic device includes a camera and a TOF sensor having a transmitter and a receiver. The shielding structure includes a base, a shutter movably connected with the base, and a barrier movably connected with the base. At least a part of the barrier is disposed between the transmitter and the receiver, and the barrier may block a signal transmitted by the transmitter. An elastic member is fixed on the base. When the shutter is moved to abut the barrier, the barrier is pushed to press the elastic member, wherein the elastic member is deformed allowing at least a portion of the shutter disposing and abutting on the barrier, and the camera and the TOF sensor may be covered by the shutter at the same time.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 2, 2024
    Inventor: YAO-WEN CHANG
  • Publication number: 20240145511
    Abstract: An image sensor includes a first sensing unit. The first sensing unit includes a pair of photodiodes formed in a substrate and spaced by a deep trench isolation structure, an outer grid over the pair of photodiodes, a color filter filled in the outer grid, and an inner grid disposed in the color filter. The color filter overlaps the pair of photodiodes. The inner grid includes a first spacer, wherein the first spacer is rotated relative to the deep trench isolation structure.
    Type: Application
    Filed: October 26, 2022
    Publication date: May 2, 2024
    Inventors: Jian-Wen LUO, Yu-Chi CHANG, Zong-Ru TU, Po-Hsiang WANG
  • Publication number: 20240145398
    Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cheng-Liang HSU, Wan-Rou CHEN, Hsin-Yin CHANG, Tsung-Li LIN, Hsiu-Jung LI, Chiu-Lien LI, Fu-Quan XU, Yi-Wen LIU, Chih-Chieh SUN
  • Publication number: 20240141035
    Abstract: An anti-IL-22 antibody or antibody fragment that binds to both human IL-22 and a mammalian IL-22 as well as modified anti-IL-22 antibodies and antibody fragments. Pharmaceutical compositions and kits comprising the antibody or antibody fragment are also provided. Also provided are methods for treatment of various IL-22 mediated conditions and diseases.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Applicant: BioAtla, Inc.
    Inventors: Jay M. Short, Gerhard Frey, Hwai Wen Chang, William Boyle
  • Patent number: 11973040
    Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yang Hsieh, Chien-Chang Lee, Chia-Ping Lai, Wen-Chung Lu, Cheng-Kang Huang, Mei-Shih Kuo, Alice Huang
  • Patent number: 11970387
    Abstract: A micro-electro mechanical system (MEMS) device includes a MEMS substrate, at least one movable element laterally confined within a matrix layer that overlies the MEMS substrate, and a cap substrate bonded to the matrix layer through bonding material portions. A first movable element selected from the at least one movable element is located inside a first chamber that is laterally bounded by the matrix layer and vertically bounded by a first capping surface that overlies the first movable element. The first capping surface includes an array of downward-protruding bumps including respective portions of a dielectric material layer. Each of the downward-protruding bumps has a vertical cross-sectional profile of an inverted hillock. The MEMS device can include, for example, an accelerometer.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-wen Cheng, Chi-Hang Chin, Kuei-Sung Chang
  • Patent number: 11973048
    Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: April 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: An-Nong Wen, Ching-Han Huang, Ching-Ho Chang
  • Patent number: 11973050
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu Lin, Yao-Wen Chang, Chia-Wen Zhong, Yen-Liang Lin
  • Publication number: 20240135745
    Abstract: An electronic device has a narrow viewing angle state and a wide viewing angle state, and includes a panel and a light source providing a light passing through the panel. In the narrow viewing angle state, the light has a first relative light intensity and a second relative light intensity. The first relative light intensity is the strongest light intensity, the second relative light intensity is 50% of the strongest light intensity, the first relative light intensity corresponds to an angle of 0°, the second relative light intensity corresponds to a half-value angle, and the half-value angle is between ?15° and 15°. In the narrow angle state, a third relative light intensity at each angle between 20° and 60° or each angle between ?20° and ?60° is lower than 20% of the strongest light intensity.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Applicant: InnnoLux Corporation
    Inventors: Kuei-Sheng Chang, Po-Yang Chen, Kuo-Jung Wu, I-An Yao, Wei-Cheng Lee, Hsien-Wen Huang
  • Publication number: 20240136864
    Abstract: A wireless power transmission device includes a transmission device and a control device. The control device generates a driving signal to the transmission device in a first soft-start period, so as to drive the transmission device. The control device measures an energy message generated by the transmission device to generate a measurement result in a measurement period, and calculates a signal parameter according to the measurement result. The control device accordingly generates a carrier signal according to the signal parameter obtained by the measurement period in a second soft-start period. In a transmission period, the carrier signal is transmitted to the wireless power-receiving device through the transmission device. The energy message is generated by the transmission device in response to a distance between the transmission device and the wireless power-receiving device.
    Type: Application
    Filed: January 6, 2023
    Publication date: April 25, 2024
    Inventors: Fu-Chi LIN, Po-Chang CHEN, Wen-Ti LO
  • Publication number: 20240136316
    Abstract: A semiconductor package includes a conductive pillar and a solder. The conductive pillar has a first sidewall and a second sidewall opposite to the first sidewall, wherein a height of the first sidewall is greater than a height of the second sidewall. The solder is disposed on and in direct contact with the conductive pillar, wherein the solder is hanging over the first sidewall and the second sidewall of conductive pillar.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiang-Jui Chu, Ching-Wen Hsiao, Hao-Chun Liu, Ming-Da Cheng, Young-Hwa Wu, Tao-Sheng Chang
  • Publication number: 20240134239
    Abstract: A display device including a substrate, a cholesteric liquid crystal layer, and a transparent electrode layer that are sequentially stacked is provided. The cholesteric liquid crystal layer includes cholesteric liquid crystal molecules and a plurality of transparent photoresist structures. Each of the transparent photoresist structures is a closed structure, and the cholesteric liquid crystal molecules are respectively accommodated in a plurality of patterned areas respectively surrounded by the transparent photoresist structures, so as to form a plurality of cholesteric liquid crystal patterns. The transparent electrode layer includes a plurality of sub-electrodes. The cholesteric liquid crystal patterns are respectively driven by the sub-electrodes. An orthogonal projection of each of the transparent photoresist structures on the substrate falls in an orthogonal projection of a corresponding sub-electrode of the sub-electrodes on the substrate.
    Type: Application
    Filed: October 22, 2023
    Publication date: April 25, 2024
    Applicant: AUO Corporation
    Inventors: Chun-Han Lee, Chien-Chuan Chen, Ju-Wen Chang, Hsin Chiang Chiang, Peng-Yu Chen
  • Patent number: 11963969
    Abstract: Provided is a pharmaceutical composition including gastrodin and a use thereof for the prevention or the treatment of amyotrophic lateral sclerosis. The pharmaceutical composition is effective in reducing neuronal axon degeneration and neurofibromin accumulation, improving symptoms of amyotrophic lateral sclerosis and extending life of patients of amyotrophic lateral sclerosis.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: April 23, 2024
    Assignee: BUDDHIST TZU CHI MEDICAL FOUNDATION
    Inventors: Chia-Yu Chang, Shinn-Zong Lin, Hsiao-Chien Ting, Hui-I Yang, Horng-Jyh Harn, Hong-Lin Su, Ching-Ann Liu, Yu-Shuan Chen, Tzyy-Wen Chiou, Tsung-Jung Ho