Abstract: One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure over a substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A bond pad structure is over the interconnect structure, a first masking layer is over the bond pad structure, and a second masking layer is over the first masking layer. The second masking layer contacts opposing outermost sidewalls of the bond pad structure and the first masking layer. A conductive bump vertically extends through the first masking layer and the second masking layer to contact the bond pad structure.

Abstract: A tray for storing biological fluid collection containers including a body comprising an upper surface comprising a perimeter portion having an outer perimeter and an inner perimeter, and a recess extending downwardly from and surrounded by the inner perimeter of the perimeter portion. The recess is divided into a plurality of wells, each well adapted to receive at least a portion of a biological fluid collection container, and the tray comprises molded plant-based pulp. The tray may further comprise a base defining a compartment that receives the body. Also, a tray for storing biological fluid collection containers including a container body comprising a plurality of interconnected wells, each well adapted to receive at least a portion of a biological fluid collection container, and a base defining a compartment adapted to receive the container body. The container body and/or the base comprises molded plant-based pulp.

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

Abstract: The present disclosure is directed towards an integrated chip including a first memory cell overlying a substrate. The first memory cell comprises a first data storage layer. A second memory cell is adjacent to the first memory cell. A dielectric layer is disposed laterally between the first memory cell and the second memory cell. An air gap is disposed within the dielectric layer. The air gap is spaced laterally between the first memory cell and the second memory cell.

Abstract: The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dl along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<Dl; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.

Abstract: The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dl along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<Dl; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes the operations as follows. A hard mask (HM) layer is formed over a dielectric layer over a substrate. A plurality of mandrels are formed over the HM layer. A spacer layer including a plurality of trenches between the mandrels is formed over the HM layer and the mandrels. A first and a second portion of the trenches is filled by a first and a second block material, respectively. A third portion of the trenches is free from filled by these block materials. At least a first opening is formed in the spacer layer. At least a second opening is formed by removing a portion of the mandrels. The HM layer is etched through the first and the second openings. The dielectric layer is patterned. A plurality of conductive lines are formed in the patterned dielectric layer.

Abstract: The present disclosure is directed towards an integrated chip including a first memory cell overlying a substrate. The first memory cell comprises a first data storage layer. A second memory cell is adjacent to the first memory cell. A dielectric layer is disposed laterally between the first memory cell and the second memory cell. An air gap is disposed within the dielectric layer. The air gap is spaced laterally between the first memory cell and the second memory cell.

Abstract: A metal grid within a trench isolation structure on the back side of an image sensor is coupled to a contact pad so that a voltage on the metal grid is continuously variable with a voltage on the contact pad. One or more conductive structures directly couple the metal grid to a contact pad. The conductive structures may bypass a front side of the image sensor. A bias voltage on the metal grid may be varied through the contact pad whereby a trade-off between reducing cross-talk and increasing quantum efficiency may be adjusted dynamically in accordance with the application of the image sensor, its environment of use, or its mode of operation.

Abstract: In some embodiments, the present disclosure relates to a process tool that includes a chamber housing defining a processing chamber. Within the processing chamber is a wafer chuck configured to hold a substrate. Further, a bell jar structure is arranged over the wafer chuck such that an opening of the bell jar structure faces the wafer chuck. A plasma coil is arranged over the bell jar structure. An oxygen source coupled to the processing chamber and configured to input oxygen gas into the processing chamber.

Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.

Abstract: A memory structure includes a first memory array having bit lines; a second memory array having bit lines; a first sense amplifier connected to a first bit line of the first memory array and a first bit line of the second memory array; and a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array. The second bit line of the first memory array is adjacent to the first bit line of the first memory array, and the second bit line of the second memory array is adjacent to the first bit line of the second memory array.

Abstract: In some embodiments, an integrated circuit (IC) device includes an active semiconductor layer, a circuitry formed within the active semiconductor layer, a region including conductive layers formed in a back-end-of-line (BEOL) layer above the active semiconductor layer, and a memory module formed in the BEOL layer. The memory device includes a three-dimensional array of memory cells, each adapted to store a weight value, and adapted to generate at each memory cell a signal indicative of a product between the stored weight value and an input signal applied to the memory cell. The memory module is further adapted to transmit the product signals from the memory cell simultaneously in the direction of the active semiconductor layer.

Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

Abstract: The present disclosure relates to an image sensor having an image sensing element surrounded by a BDTI structure, and an associated method of formation. In some embodiments, a first image sensing element and a second image sensing element are arranged next to one another within an image sensing die. A pixel dielectric stack is disposed along a back of the image sensing die overlying the image sensing elements. The pixel dielectric stack includes a first high-k dielectric layer and a second high-k dielectric layer. The BDTI structure is disposed between the first image sensing element and the second image sensing element and extends from the back of the image sensor die to a position within the image sensor die. The BDTI structure includes a trench filling layer surrounded by an isolation dielectric stack. The pixel dielectric stack has a composition different from that of the isolation dielectric stack.

Abstract: A electrode plate cutting method includes: obtaining an offset distance between a detection reference and a cutting position on an electrode plate; obtaining, based on the offset distance and a distance between the detection reference and a cutting device, an actual distance between the cutting position and the cutting device; and obtaining, based on the actual distance, a cutting time point for the cutting position to be conveyed to the cutting device, so that the cutting device cuts at the cutting position. Obtaining the offset distance between the detection reference and the cutting position of the electrode plate is equivalent to obtaining a deviation from the detection reference caused during transferring of the electrode plate.

Abstract: A foaming apparatus for a paper container (90), including: a main body (10), a delivery mechanism, a plurality of supports (30), a heating mechanism (40), a cooling mechanism (50), a feeding mechanism (60), and a pick-up mechanism (70). The main body (10) is divided into a feeding and pick-up area (13), a preheating area (14), a heating area (15) and a cooling area (16) on a horizontal plane; the delivery mechanism includes a chain (21) in closed circulation; each of the supports (30) is provided with a supporting portion (32) and a base (31); the heating mechanism (40) is disposed on the preheating area (14) and the heating area (15) so as to heat same; the cooling mechanism (50) is disposed on the cooling area (16) so as to cool same; the feeding mechanism (60) and the pick-up mechanism (70) are separately disposed above the feeding and pick-up area (13).