Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.

Abstract: A polypeptide having a heavy chain variable region and/or light chain variable region that specifically binds to Ror2 protein as well as antibodies and antibody fragments containing the heavy chain variable region and/or the light chain variable region that bind to Ror2 protein. Pharmaceutical compositions and kits comprising the polypeptide or antibodies and antibody fragments containing the polypeptide are also provided.

Abstract: A cathode plate and a battery are described. The cathode plate includes: a main body with a cuboid shape, which is formed by stacking a cathode active material layer and a cathode current collector in a first direction and has four side faces and two end faces facing each other in the first direction, and the four side faces being a first side face to a fourth side face; a cathode tab, formed by the cathode current collector extending from the first side face to an outside of the main body; and an insulating layer, formed on and covering 95% or more of the second side face to the fourth side face.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: A polymer is formed by capping a copolymer-graft-polylactone with an alcohol, wherein the copolymer is copolymerized from an anhydride monomer with a double bond, a monomer with a double bond, and an initiator. The polymer can be mixed with an organic solvent and pigment powder to form a dispersion. The dispersion can be mixed with a binder to form a paint.

Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

Abstract: A system of controlling a vehicle may include a sensor and a controller, in which the sensor may be configured to sense vehicle operation state information, and the controller may be configured to determine whether a vehicle is running on a dangerous road based on the sensed vehicle operation state information, determine whether there is a possibility that a vehicle driving state will cause a failure of a driving system based on the sensed vehicle operation state information in response to determining that the vehicle is running on the dangerous road, and decide that torque control of the vehicle.

Abstract: A semiconductor device, including a substrate, a first source/drain region, a second source/drain region, and a gate structure, is provided. The substrate has an extra body portion and a fin protruding from a top surface of the substrate, wherein the fin spans the extra body portion. The first source/drain region and the second source/drain region are in the fin. The gate structure spans the fin, is located above the extra body portion, and is located between the first source/drain region and the second source/drain region.

Abstract: A photo-detecting device includes a first semiconductor layer with a first dopant, a light-absorbing layer, a second semiconductor layer, and a semiconductor contact layer. The second semiconductor layer is located on the first semiconductor layer and has a first region and a second region, the light absorbing layer is located between the first semiconductor layer and the second semiconductor layer and has a third region and a fourth region, the semiconductor contact layer contacts the first region. The first region includes a second dopant and a third dopant, the second region includes second dopant, and the third region includes third dopant. The semiconductor contact layer has a first thickness greater than 50 ? and smaller than 1000 ?.

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: Monoclonal antibodies against human Mac-1 are provided. These antibodies can bind to different states of Mac-1 so as to alter the biofunctions of Mac-1. These antibodies can modulate Th1/Th2 cytokine secretions by TLR-activated immune cells and can be used for the treatments of diseases related to acute and chronic inflammatory disorders, such as infectious diseases, and cancers.

Abstract: A method for forming a semiconductor structure includes the steps of forming a stacked structure on a substrate, forming an insulating layer on the stacked structure, forming a passivation layer on the insulating layer, performing an etching process to form an opening through the passivation layer and the insulating layer to expose a portion of the stacked structure and an extending portion of the insulating layer, and forming a contact structure filling the opening and directly contacting the stacked structure, wherein the extending portion of the insulating layer is adjacent to a surface of the stacked structure directly contacting the contact structure.

Abstract: A transistor includes: a substrate; a first fin and a second fin protruding upwardly from a top surface of the substrate, wherein the first fin and the second fin are concentric, and each of the first fin and the second fin comprises a first straight section, a second straight section in parallel with the first straight section, a first curved section, and a second curved section; a first drain and a second drain; a first source and a second source; a first curved channel and a second curved channel located at the first curved section of the first fin and the first curved section of the second fin, respectively; and a third curved channel and a fourth curved channel located at the second curved section of the first fin and the second curved section of the second fin, respectively.

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

Abstract: Embodiments of the invention overcome the shortcomings of prior technologies by infusing nanocellulose in a fibrillated form to enhance the properties of cellulose pulp. These properties may include, for example, the mechanical and barrier properties, i.e., tensile strength, liquid, and gas impermeability such as oxygen, carbon dioxide, and oil, can be improved substantially. Another embodiment of the invention further provide a fibrillated cellulose composite material that include a blend of fibrillated cellulose and polymers to create improved properties over cellulose-based materials. The composite material further may be generally free of chemical additives to enhance the above properties.

Abstract: The present invention provides antibody or the antigen-binding portion thereof bind to carbohydrate antigen, such as Globo series antigens (e.g. Globo H, SSEA-4 or SSEA-3). Also disclosed herein are pharmaceutical compositions and methods for the inhibition of cancer cells in a subject in need thereof. The pharmaceutical compositions comprise an antibody or an antigen-binding portion thereof and at least one pharmaceutically acceptable carrier.

Abstract: A foamable resin composition comprising: (meth)acrylate oligomer, which accounts for 10-40 wt % of the foamable resin composition; (meth)acrylate monomer, which accounts for 35-80 wt % of the foamable resin composition; a photocuring initiator, which accounts for 1-5 wt % of the foamable resin composition; and a foaming agent, which accounts for 3-20 wt % of the foamable resin composition; wherein the foamable resin composition has a specific gravity of 0.10-1.05 g/cm3 after photocuring and thermal foam expansion for 15-20 minutes at 120° C. The aforementioned foamable resin composition can become a low specific gravity (0.10-1.05 g/cm3) material after photocuring and thermal foam expansion, then can expand the application in 3D printing, and manufacture of plastic products, such as shoe soles, coasters, floats, various types of protective gear and the like.

Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.