Abstract: A computing device performs a method of decoding video data by reconstructing a luma block corresponding to a chroma block; searching a sub-group of a plurality of reconstructed neighboring luma samples in a predefined order to identify a maximum luma sample and a minimum luma sample; computing a down-sampled maximum luma sample corresponding to the maximum luma sample; computing a down-sampled minimum luma sample corresponding to the minimum luma sample; generating a linear model using the down-sampled maximum luma sample, the down-sampled minimum luma sample, the first reconstructed chroma sample, and the second reconstructed chroma sample; computing down-sampled luma samples from luma samples of the reconstructed luma block, wherein each down-sampled luma sample corresponds to a chroma sample of the chroma block; and predicting chroma samples of the chroma block by applying the liner model to the corresponding down-sampled luma samples.

Abstract: A method of building a characteristic model includes: acquiring raw electrical data from a measurement system outside one or more processing units; acquiring operational state-related data from an information collector inside the one or more processing units; performing a data annealing process on the raw electrical data and the operational state-related data to obtain and purified electrical data and purified operational state-related data; and performing a machine learning (ML)-based process to build the characteristic model based on the purified electrical data and the purified operational state-related data.

Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.

Abstract: A phantom-free calibration method for a computerized tomography scan has the steps of: scanning a plurality of homogeneous human tissues with a computerized tomography scanner and obtaining homogeneous human tissue scan information; scanning a tissue to be tested with the computerized tomography scanner and obtaining tissue to be tested scan information; calculating a spectral characteristic parameter of the computerized tomography scanner with a computing device using a model, wherein a standard tissue parameter of the homogeneous human tissues and the human tissue scan information are used in the model; and calculating a tissue parameter of the tissue to be tested with the computing device using the model, wherein the spectral characteristic parameter and the tissue to be tested scan information are inputted in the model. The phantom-free calibration method makes the tissue parameters of the tissue to be tested more accurate and the calibration process easier and more convenient.

Abstract: A structured-light three-dimensional (3D) scanning system includes a projector that emits a projected light with a predetermined pattern onto an object; an image capture device that generates a captured image according to a reflected light reflected from the object, the predetermined pattern of the projected light being distorted due to 3D shape of the object, thereby resulting in a distorted pattern; a depth decoder that converts the distorted pattern into a depth map representing the 3D shape of the object; and a depth fusion device that generates a fused depth map according to at least two different depth maps associated with the object.

Abstract: Methods, apparatuses, and non-transitory computer-readable storage mediums are provided for decoding a video signal. The method includes obtaining a first reference picture I associated with a video block, obtaining control point motion vectors (CPMVs) of an affine coding block based on the video block, obtaining prediction samples I(i, j) of the affine coding block, deriving PROF prediction sample refinements of the affine coding block based on the PROF, receiving an LIC flag that indicates whether the LIC is applied to the affine coding block, deriving, and when the LIC is applied, LIC weight and offset based on neighboring reconstructed samples of the affine coding block and their corresponding reference samples in the first reference picture, and obtaining final prediction samples of the affine coding block based on the PROF prediction sample refinements and the LIC weight and offset.

Abstract: Method and apparatus of video coding are disclosed. According to one method, in the decoder side, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block when the neighboring block satisfies one or more conditions. An MPM (Most Probable Mode) list is derived based on information comprising at least one of neighboring Intra modes. A current Intra mode is derived utilizing the MPM list. The current luma block is decoded according to the current Intra mode According to another method, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block if the neighboring block is coded in BDPCM (Block-based Delta Pulse Code Modulation) mode, where the predefined Intra mode is set to horizontal mode or vertical mode depending on prediction direction used by the BDPCM mode.

Abstract: The present disclosure relates to a power regulating unit and a transport refrigeration device using the same, and belongs to the technical field of power supplies. The power regulating unit of the present disclosure comprises: a rectifier module configured to perform a rectification operation on an AC input to obtain a first DC signal; a controller configured to control the rectification operation of the rectifier module based on corresponding parameter information for reflecting fluctuations of the AC input to prevent the first DC signal obtained from being affected by the fluctuations; a first output port configured to output the first DC signal; a first DC-DC conversion module configured to convert the first DC signal into a second DC signal; and a second output port configured to output the second DC signal. The power regulating unit of the present disclosure can provide multi-mode DC outputs and the DC outputs are stable.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: A battery module includes an insulating base, a pair of electrodes and multiple battery packs. Each electrode is installed to the insulating base and has a bridge portion and a wire connecting part exposed from the insulating base, and a pair of lugs is extended smoothly from each battery pack, and an end of at least a part of the lugs is attached to each bridge portion correspondingly. Therefore, the lug is not being twisted or deformed easily, and the battery module may have good conductive efficiency, long service life, and convenience of changing the battery pack.

Abstract: A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.

Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.

Abstract: A normally closed disc clamp system includes a housing with a rotating disc, a brake ring and a pressure-enhancing ring arranged therein. When only a first chamber is supplied with fluid, the fluid pushes the brake ring to release the rotating disc. When only a second chamber is fed with fluid, the fluid pushes the brake ring to keep the rotating disc in the braking state, and pushes the pressure-enhancing ring to compress an elastic unit. The energy generated by the compression of the elastic unit acts on the brake ring through the fluid, so that the brake ring achieves a double pressurization effect. If the action of the fluid fails, the brake ring can still provide a braking effect to the rotating disc through the elastic unit to improve operational safety. Further, the present invention further provides a rotating table using the normally closed disc clamp system.

Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

Abstract: A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.

Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.

Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (Al) or formula (A2): Zr12O8(OH)14(RCO2)18??Formula (A1); or Hf6O4(OH)6(RCO2)10??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.

Abstract: The present disclosure provides a matrix device and an operation method thereof. The matrix device includes a transpose circuit and a memory. The transpose circuit is configured to receive a first element string representing a native matrix from a matrix source, wherein all elements in the native matrix are arranged in the first element string in one of a “row-major manner” and a “column-major manner”. The transpose circuit transposes the first element string into a second element string, wherein the second element string is equivalent to an element string in which all elements of the native matrix are arranged in another one of the “row-major manner” and the “column-major manner”. The memory is coupled to the transpose circuit to receive the second element string.

Abstract: A media docking device includes an input module, an output module and a processing module. The input module is electrically connected to a media source device for receiving media data. The output module is electrically connected to a media play device. The processing module determines if an instruction is received from the media source device or a remote device. If the instruction is not received, the processing module transfers the media data to the output module to transmit to the media play device. If the instruction is received, the processing module limits a transmission of the media data according to the instruction, such that the media data will not be completely played by the media play device.

Abstract: A method for detecting defects on a wafer including the steps of obtaining a reference image of a chip pattern formed on a reference wafer, using a computer algorithm to analyze the reference image to produce a division map for the chip pattern; setting respective thresholds for divisions of the division map, obtaining a comparison data between a test image of the chip pattern formed on a test wafer and the reference image, using the division map and the thresholds to examine the comparison data to identify a defect in the test image.