Patents by Inventor Wen-Cheng Chen

Wen-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250107184
    Abstract: A semiconductor device structure and methods of forming the same are described. The method includes forming a fin structure from a substrate, depositing a first semiconductor material on a first semiconductor layer of the fin structure, depositing a second semiconductor material on the first semiconductor material, depositing an interlayer dielectric layer over the second semiconductor material, forming an opening in the interlayer dielectric layer to expose the second semiconductor material, and performing a dopant implantation process to form a doped region. The doped region includes a first portion of the second semiconductor material. Then, the method further includes performing an amorphization process to form an amorphous region, and the amorphous region includes a second portion of the second semiconductor material. The method further includes performing an annealing process to recrystallize the amorphous region.
    Type: Application
    Filed: January 3, 2024
    Publication date: March 27, 2025
    Inventors: Wen-Yen CHEN, Min-Tsang LI, Liang-Yin CHEN, Chi On CHUI, Chia-Cheng CHEN
  • Publication number: 20250098346
    Abstract: An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.
    Type: Application
    Filed: January 19, 2024
    Publication date: March 20, 2025
    Inventors: Wen-Chung Chen, Chia-Yu Wei, Kuo-Cheng Lee, Cheng-Hao Chiu, Hsiu Chi Yu, Hsun-Ying Huang, Ming-Hong Su
  • Publication number: 20250098237
    Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a first transistor. The first transistor includes a first gate structure wrapping around a plurality of first nanostructures disposed over a substrate, a first source/drain feature electrically coupled to a topmost nanostructure of the plurality of first nanostructures and isolated from a bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer, and a first semiconductor layer disposed between the substrate and the first source/drain feature, wherein the first source/drain feature is in direct contact with a top surface of the first semiconductor layer.
    Type: Application
    Filed: January 4, 2024
    Publication date: March 20, 2025
    Inventors: Jung-Hung Chang, Shih-Cheng Chen, Tsung-Han Chuang, Wen-Ting Lan, Chia-Cheng Tsai, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20250098219
    Abstract: A device includes: a substrate having a semiconductor fin; a stack of semiconductor channels on the substrate and positioned over the fin; a gate structure wrapping around the semiconductor channels; a source/drain abutting the semiconductor channels; an inner spacer positioned between the stack of semiconductor channels and the fin; an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.
    Type: Application
    Filed: February 15, 2024
    Publication date: March 20, 2025
    Inventors: Jung-Hung CHANG, Shih-Cheng CHEN, Tsung-Han CHUANG, Fu-Cheng CHANG, Wen-Ting LAN, Chia-Cheng TSAI, Kuo-Cheng CHIANG, Chih-Hao WANG, Wang-Chun Huang, Shi-Syuan Huang
  • Publication number: 20250070092
    Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Wen-Tuo Huang, Chia-Sheng Lin, Wei Chuang Wu, Shih Kuang Yang, Chung-Jen Huang, Shun-Kuan Lin, Chien Lin Liu, Ping-Tzu Chen, Yung Chun Tu
  • Publication number: 20250071935
    Abstract: A heat dissipation assembly is disclosed and includes a fan, a vapor chamber and a heat dissipation fin set. The fan includes a fan frame, an impeller and a fan cover. The impeller is disposed on the fan frame and accommodated in an accommodation space. The impeller includes plural metal blades and a hub, and the plural metal blades are radially arranged on the periphery of the hub to form a dense-metal-blade impeller. The fan cover is assembled with the fan frame to form an outlet, and the fan cover includes an inlet. The vapor chamber includes an upper plate and a lower plate assembled with each other. The upper plate or the lower plate is connected to the fan cover, and the vapor chamber and the fan cover are coplanar. The heat dissipation fin set is connected to the lower plate and spatially corresponding to the outlet.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Inventors: Chin-Ting Chen, Chih-Wei Yang, Shu-Cheng Yang, Che-Wei Chang, Wen-Cheng Huang, Chin-Hung Lee, Chih-Wei Chan
  • Publication number: 20250072067
    Abstract: A semiconductor structure includes an isolation structure in a substrate, a metal gate structure over the substrate and a portion of the isolation structure, a spacer at sidewalls of the metal gate structure, epitaxial source/drain structure at two sides of the metal gate structure, and a protection layer over the isolation structure. The protection layer and the spacer include a same material.
    Type: Application
    Filed: August 25, 2023
    Publication date: February 27, 2025
    Inventors: SHIH-CHENG CHEN, WEN-TING LAN, JUNG-HUNG CHANG, CHIA-CHENG TSAI, KUO-CHENG CHIANG
  • Patent number: 12235543
    Abstract: An electronic device is provided. The electronic device includes a frame, a working panel, a case, and an adhesive material. The frame includes a side wall and a back plate. The working panel is disposed on the back plate. The case is disposed on the frame and adjacent to the working panel. The adhesive material is disposed on the case. The side wall has an outer surface facing away from the working panel. In a cross-section view of the electronic device, a portion of the adhesive material is in contact with the outer surface of the side wall of the frame, and a length of the adhesive material is greater than or equal to 50% of a length of the side wall of the frame along an extension direction.
    Type: Grant
    Filed: March 19, 2024
    Date of Patent: February 25, 2025
    Assignee: INNOLUX CORPORATION
    Inventors: Wen-Cheng Huang, Ting-Sheng Chen, Chia-Chun Yang, Chin-Cheng Kuo
  • Patent number: 12227619
    Abstract: The present invention provides a polyimide-based copolymer and electronic component and field effect transistor comprising the same. The polyimide-based copolymer comprises a copolymer of dianhydride and heterocyclic diamine, wherein the heterocyclic diamine has two benzene rings, and there are two ether bonds, two thioether bonds, or one ether bond and one thioether bond between the two benzene rings. The novel polyimide-based copolymer of the invention has excellent thermal-mechanical stability, has potential application prospects, and can be used as a substrate for flexible electronics.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: February 18, 2025
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Wen-Chang Chen, Mitsuru Ueda, Chun-Kai Chen, Yan-Cheng Lin
  • Patent number: 12222253
    Abstract: A medicament delivery device development evaluation system is presented having a dummy medicament delivery device comprising at least one force sensor configured to detect an external force applied to the dummy medicament delivery device, processing circuitry configured to receive force measurements from the force sensor, and a storage medium configured to store the force measurements received by the processing circuitry.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: February 11, 2025
    Assignee: SHL MEDICAL AG
    Inventors: Chun Chang, Chia Cheng Lin, Sheng-wei Lin, Hsueh-Yi Chen, Yiju Chen, Wen-Sheng Chien
  • Publication number: 20250031458
    Abstract: A semiconductor structure is provided in the present invention, including a substrate, a deep N-well formed in the substrate, a first well formed in the deep N-well, a first gate formed on the first well, a first source and a first drain formed respectively at two sides of the first gate in the first well, a first doped region formed in the first well, and a metal interconnect electrically connected with the first source and the first doped region, wherein an area of the deep N-well multiplied by a first parameter is a first factor, an area of the first gate multiplied by a second parameter is a second factor, and an area of the metal interconnect divided by a sum of the first factor and the second factor is less than a specification value.
    Type: Application
    Filed: September 5, 2023
    Publication date: January 23, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Te Lin, Wen-Chun Chang, Sung-Nien Kuo, Tzu-Chun Chen, Kuan-Cheng Su
  • Publication number: 20250026903
    Abstract: A matte polyester film and a method for manufacturing the same are provided. The method for manufacturing the matte polyester film includes: providing a recycled polyester material; physically regenerating a part of the recycled polyester material to form physically regenerated polyester chips having a first intrinsic viscosity; chemically regenerating another part of the recycled polyester material to form chemically regenerated polyester chips having a second intrinsic viscosity less than the first intrinsic viscosity; mixing matte regenerated polyester chips, the physically regenerated polyester chips, and the chemically regenerated polyester chips according to a predetermined intrinsic viscosity so as to form a polyester masterbatch material; melting and then extruding the polyester masterbatch material to obtain the matte polyester film having the predetermined intrinsic viscosity.
    Type: Application
    Filed: October 8, 2024
    Publication date: January 23, 2025
    Applicant: NAN YA PLASTICS CORPORATION
    Inventors: Wen-Cheng Yang, Te-Chao Liao, Chun-Cheng Yang, Chia-Yen Hsiao, Hao-Sheng Chen
  • Patent number: 12206012
    Abstract: A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl3)2CH2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu, Szu-Ying Chen
  • Patent number: 11874166
    Abstract: The present application discloses a light sensor circuit, which comprises a photodiode and a capacitor unit. The cathode of the photodiode is controlled by a capacitive unit to maintain the same or close voltage level as the anode of the photodiode, which significantly reduces the effect of the dark current of the photodiode. Thus, the light sensor circuit can effectively maintain the performance and accuracy of an analog-to-digital converter applying the light sensor circuit. The circuit design difficulty and manufacturing cost are also significantly reduced.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: January 16, 2024
    Assignee: Sensortek Technology Corp.
    Inventors: Wen-Cheng Chen, Kai-Hsiang Chan, Sheng-Wen Huang
  • Publication number: 20230243697
    Abstract: The present application discloses a light sensor circuit, which comprises a photodiode and a capacitor unit. The cathode of the photodiode is controlled by a capacitive unit to maintain the same or close voltage level as the anode of the photodiode, which significantly reduces the effect of the dark current of the photodiode. Thus, the light sensor circuit can effectively maintain the performance and accuracy of an analog-to-digital converter applying the light sensor circuit. The circuit design difficulty and manufacturing cost are also significantly reduced.
    Type: Application
    Filed: October 6, 2022
    Publication date: August 3, 2023
    Inventors: WEN-CHENG CHEN, KAI-HSIANG CHAN, SHENG-WEN HUANG
  • Patent number: 11150404
    Abstract: A method includes bonding an electronic die to a photonic die. The photonic die includes an opening. The method further includes attaching an adapter onto the photonic die, with a portion of the adapter being at a same level as a portion of the electronic die, forming a through-hole penetrating through the adapter, with the through-hole being aligned to the opening, and attaching an optical device to the adapter. The optical device is configured to emit a light into the photonic die or receive a light from the photonic die.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Hui Huang, Jui Hsieh Lai, Tien-Yu Huang, Wen-Cheng Chen, Yushun Lin
  • Patent number: 10592426
    Abstract: A method for accessing a physical region page (PRP) list includes obtaining a PRP address of a PRP list, in which the PRP address has M bits; performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain a page base address if the PRP address is within a page boundary; and performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain next PRP address pointer if the PRP address reaches the page boundary. N is an integer, and M is an integer larger than N.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: March 17, 2020
    Assignee: ASMEDIA TECHNOLOGY INC.
    Inventor: Wen-Cheng Chen
  • Publication number: 20190369329
    Abstract: A method includes bonding an electronic die to a photonic die. The photonic die includes an opening. The method further includes attaching an adapter onto the photonic die, with a portion of the adapter being at a same level as a portion of the electronic die, forming a through-hole penetrating through the adapter, with the through-hole being aligned to the opening, and attaching an optical device to the adapter. The optical device is configured to emit a light into the photonic die or receive a light from the photonic die.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 5, 2019
    Inventors: Sung-Hui Huang, Jui Hsieh Lai, Tien-Yu Huang, Wen-Cheng Chen, Yushun Lin
  • Patent number: 10459159
    Abstract: A method includes bonding an electronic die to a photonic die. The photonic die includes an opening. The method further includes attaching an adapter onto the photonic die, with a portion of the adapter being at a same level as a portion of the electronic die, forming a through-hole penetrating through the adapter, with the through-hole being aligned to the opening, and attaching an optical device to the adapter. The optical device is configured to emit a light into the photonic die or receive a light from the photonic die.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Hui Huang, Jui Hsieh Lai, Tien-Yu Huang, Wen-Cheng Chen, Yushun Lin
  • Publication number: 20190250327
    Abstract: A method includes bonding an electronic die to a photonic die. The photonic die includes an opening. The method further includes attaching an adapter onto the photonic die, with a portion of the adapter being at a same level as a portion of the electronic die, forming a through-hole penetrating through the adapter, with the through-hole being aligned to the opening, and attaching an optical device to the adapter. The optical device is configured to emit a light into the photonic die or receive a light from the photonic die.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Sung-Hui Huang, Jui Hsieh Lai, Tien-Yu Huang, Wen-Cheng Chen, Yushun Lin