Patents by Inventor Wen Cheng

Wen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8656511
    Abstract: A method for attaching a conductive particle to the apex of a probe tip comprises the steps of: moving the apex of a probe tip close to a conductive particle and applying a bias voltage between the probe tip and the conductive particle so that the conductive particle can permanently attach to the apex. The method uses only a bias voltage to transfer and attach conductive particles to the apex of a probe tip, and no surface treatment of the probe tip is required.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: February 18, 2014
    Assignee: National Tsing Hua University
    Inventors: Fan Gang Tseng, Hui Wen Cheng, Wun Yuan Jheng
  • Publication number: 20140045302
    Abstract: A submount and a manufacturing method thereof are provided. The submount, on which at least a semiconductor die is disposed, is mounted on a circuit board. The submount includes a substrate made of a conductive material or a semiconducting material, a plurality of conductive film patterns, and an insulating film pattern. A surface of the substrate includes a die-bonding area and a plurality of conductive areas. The conductive film patterns are individually distributed in the respective conductive areas. The insulating film pattern is disposed between the conductive film pattern and the insulating film pattern, but is not disposed in the die-bonding area. Furthermore, the semiconductor die is disposed in the die-bonding area and is electrically connected with the conductive film patterns. Because the insulating film pattern is not being disposed in the die-bonding area of the submount, the submount structure has improved heat transfer efficiency.
    Type: Application
    Filed: October 21, 2013
    Publication date: February 13, 2014
    Applicant: Unistars
    Inventors: Wen-Cheng Chien, Chia-Lun Tsai
  • Publication number: 20140042562
    Abstract: A device includes a Micro-Electro-Mechanical System (MEMS) wafer having a MEMS device therein. The MEMS device includes a movable element, and first openings in the MEMS wafer. The movable element is disposed in the first openings. A carrier wafer is bonded to the MEMS wafer. The carrier wafer includes a second opening connected to the first openings, wherein the second opening includes an entry portion extending from a surface of the carrier wafer into the carrier wafer, and an inner portion wider than the entry portion, wherein the inner portion is deeper in the carrier wafer than the entry portion.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng, Te-Hao Lee, Chung-Hsien Lin
  • Publication number: 20140043261
    Abstract: A touch panel includes a first plate, an antenna component and a decoration layer. A touch input area and a peripheral area aside to the input area are defined on the first plate. The antenna component is located at the peripheral area. The decoration layer is located at the peripheral area and hides the antenna component from view.
    Type: Application
    Filed: May 28, 2013
    Publication date: February 13, 2014
    Inventors: Kuei-Ching Wang, Wen-Cheng Yu
  • Patent number: 8647962
    Abstract: The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Martin Liu, Richard Chu, Hung Hua Lin, Hsin-Ting Huang, Jung-Huei Peng, Yuan-Chih Hsieh, Lan-Lin Chao, Chun-Wen Cheng, Chia-Shiung Tsai
  • Patent number: 8648401
    Abstract: A semiconductor memory device includes a first ferromagnetic layer magnetically pinned and positioned within a first region of a substrate; a second ferromagnetic layer approximate the first ferromagnetic layer; and a barrier layer interposed between the first ferromagnetic layer and the first portion of the second ferromagnetic layer. The second ferromagnetic layer includes a first portion being magnetically free and positioned within the first region; a second portion magnetically pinned to a first direction and positioned within a second region of the substrate, the second region contacting the first region from a first side; and a third portion magnetically pinned to a second direction and positioned within a third region of the substrate, the third region contacting the first region from a second side.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Huang Lai, Sheng-Huang Huang, Kuo-Feng Huang, Ming-Te Liu, Chun-Jung Lin, Ya-Chen Kao, Wen-Cheng Chen
  • Patent number: 8648929
    Abstract: Anti-flicker camera and image capture method are disclosed. According to the disclosed method, exposure integrals of different lines of an image sensed by a camera device are calculated. The exposure integrals are compared with reference exposure integrals of the plurality of lines, respectively, to calculate exposure integral offsets for the lines. The reference exposure integrals are estimated from at least one reference image. The positive and negative changes of the exposure integral offsets are statistically analyzed and, accordingly, it is determined whether there is light flicker from background illumination and an auto-exposure control module of the camera device is controlled based on the determination.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: February 11, 2014
    Assignee: Silicon Motion, Inc.
    Inventors: Wen-Cheng Ho, Yung-Wei Chen
  • Patent number: 8648468
    Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum -based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Richard Chu, Martin Liu, Chia-Hua Chu, Yuan-Chih Hsieh, Chung-Hsien Lin, Lan-Lin Chao, Chun-Wen Cheng, Mingo Liu
  • Publication number: 20140035970
    Abstract: A pixel includes four sub-pixels. The pixel is used to receive a plurality of signal values to display an image. The signal values are N-bit signal values, and the largest value of the signal values is (2N?1). The method of displaying the image with the pixel includes providing three color signals, generating four transformation signals corresponding to the four sub-pixels according to the values of the three color signals, and using four output signals to display the image of the pixel when the color saturation value is not larger than a first predetermined value and a fourth transformation signal of the four transformation signals is larger than other three transformation signals of the four transformation signals.
    Type: Application
    Filed: December 14, 2012
    Publication date: February 6, 2014
    Applicant: AU OPTRONICS CORP.
    Inventors: Hui Chu Ke, Sheng-Wen Cheng, Wei-Chieh Sun, Ming-Sheng Lai
  • Patent number: 8643198
    Abstract: An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: February 4, 2014
    Inventors: Wen-Cheng Chien, Ching-Yu Ni, Shu-Ming Chang
  • Publication number: 20140030075
    Abstract: An exemplary housing of a cooling fan includes a metallic base plate and a plastic bear seat. Clasps extend upwardly from the base plate. The bear seat is formed on the base plate via injection process. A bottom end of the bear seat directly contacts the base plate. The clasps are embedded in the bear seat.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 30, 2014
    Applicant: Foxconn Technology Co., Ltd.
    Inventor: Wen-Cheng CHEN
  • Publication number: 20140030860
    Abstract: A manufacturing method of tunnel oxide of NOR flash memory controls the temperature and thickness of tunnel oxide in a gate structure to prevent a channel region to change its doping concentration and range due to a high-temperature manufacturing process, so as to overcome the leakage current and improve the reliability of storing data.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 30, 2014
    Inventors: YIDER WU, YI-HSIU CHEN, WEN-CHENG LEE
  • Publication number: 20140022271
    Abstract: Provide a set of first RGB (red, green, blue) brightness levels of a set of pixels in a display panel. Generate a set of saturation levels according to the set of first RGB brightness levels. Generate a set of mapping ratios according to the set of saturation levels and the set of first RGB brightness levels. Generate a set of second RGB brightness levels according to the set of first RGB brightness levels and a minimum mapping ratio of the set of mapping ratios. Generate a set of RGBW (red, green, blue, white) brightness levels according to the set of second RGB brightness levels and a set of brightness levels of white sub-pixels of the set of RGBW brightness levels. And convert the set of RGBW brightness levels to generate a set of RGBW gray levels of the set of pixels.
    Type: Application
    Filed: September 12, 2012
    Publication date: January 23, 2014
    Applicant: AU OPTRONICS CORP.
    Inventors: Hui-Feng Lin, Sheng-Wen Cheng
  • Publication number: 20140015069
    Abstract: MEMS devices, packaged MEMS devices, and methods of manufacture thereof are disclosed. In one embodiment, a microelectromechanical system (MEMS) device includes a first MEMS functional structure and a second MEMS functional structure. An interior region of the second MEMS functional structure has a pressure that is different than a pressure of an interior region of the first MEMS functional structure.
    Type: Application
    Filed: July 13, 2012
    Publication date: January 16, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Chih Liang, Chun-Wen Cheng
  • Publication number: 20140015503
    Abstract: A boot-strap circuit for a voltage converting device includes a boot-strap capacitor; a charging module, for charging the boot-strap capacitor; and a protection module, for detecting a capacitor voltage of the boot-strap capacitor and adjusting conducting statuses of one of an upper-bridge switch and a lower-bridge switch of the voltage converting device according to the capacitor voltage and a duty cycle signal utilized for controlling conducting statuses of the upper-bridge switch and the lower-bridge switch.
    Type: Application
    Filed: October 25, 2012
    Publication date: January 16, 2014
    Applicant: ANPEC ELECTRONICS CORPORATION
    Inventor: Chieh-Wen Cheng
  • Patent number: 8629517
    Abstract: A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Chung-Hsien Lin, Chia-Hua Chu
  • Patent number: 8624790
    Abstract: The present invention relates to a porous magnetic antenna, comprising: an antenna; an insulating layer, having one side next to said antenna; and a magnetic layer, placed next to the other side of the insulating layer, separated from said antenna with a distance, and having at least one hole. The porous magnetic antenna has the advantages of shaping the field pattern, lowering the sensitivity, improving the gain value and possessing stable directionality.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: January 7, 2014
    Assignee: Mingchi University of Technology
    Inventors: Wen-Cheng Lai, Ching-Wen Hsue, Li-Ming Lo
  • Patent number: 8627243
    Abstract: Methods for optimizing conductor patterns for conductors formed by ECP and CMP processes. A method includes receiving layout data for an IC design where electrochemical plating (ECP) processes form patterned conductors in at least one metal layer over a semiconductor wafer; determining from the received layout data a global effects factor corresponding to a global pattern density; determining layout effects factors for unit grid areas corresponding to the pattern density of the at least one metal layer within the unit grid areas, determining local effects factors for each unit grid area; using a computing device, executing an ECP simulator using at least one of the global effects factor and the local effects factors, and using the layout effects factor; outputting an predicted post-ECP hump data map from the ECP simulator; and if indicated by a threshold comparison, modifying the layout data.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Lin, Yu-Wei Chou, Wen-Cheng Huang, Cheng-I Huang, Ching-Hua Hsieh
  • Patent number: 8623993
    Abstract: A series of ladder-type multifused arenes (hexacyclic, heptacyclic and nonacyclic units) and the synthesizing methods thereof are provided. The ladder-type multifused arenes are copolymerized with various electron-deficient acceptor units to afford various p-type low-band gap conjugated copolymers.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: January 7, 2014
    Assignee: National Chaio Tung University
    Inventors: Chian-Shu Hsu, Yen-Ju Cheng, Jhong-Sian Wu, Chiu-Hsiang Chen, Huan-Hsuan Chang, Yung-Lung Chen, Sheng-Wen Cheng
  • Publication number: 20140001523
    Abstract: A method of preparing an active pixel cell on a substrate includes exerting a first stress on the substrate by forming a shallow trench isolation (STI) structure in the substrate. The method further includes testing the stressed substrate using Raman spectroscopy at a plurality of locations on the stress substrate. The method further includes depositing a stress layer having a second stress on the substrate. The stress layer covers devices of the active pixel cell that are on the substrate and the devices include a photodiode next to the STI and a transistor, and the deposition of the stress layer results in the second stress being exerted on the substrate, the second stress countering the first stress.
    Type: Application
    Filed: September 4, 2013
    Publication date: January 2, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Shang HSIAO, Nai-Wen CHENG, Chung-Te LIN, Chien-Hsien TSENG, Shou-Gwo WUU