Abstract: A flash memory device and a program method thereof are provided. The flash memory device includes a memory array, a first global bit line, and a sense amplifying device. The memory array includes a first memory block having a plurality of first memory cells. In a leakage current detection operation, the sense amplifying device detects a leakage current generated by the first memory cells on the first global bit line to obtain leakage current simulation information. In a program operation, the sense amplifying device provides a reference current according to the leakage current simulation information, and compares a sensing current generated by a selected memory cell in the first memory cells on the first global bit line with the reference current to perform a program verification.

Abstract: An electronic device and a data transmission method thereof are provided. The data transmission method includes: setting dummy data having multiple dummy bits; inserting the dummy bits of the dummy data into transmission data according to an insertion type to generate encryption data; and transmitting the encryption data to a memory device.

Abstract: A memory, including a selected memory cell block and a first sense amplifying device, is provided. The selected memory cell block and the first sense amplifying device are both coupled to a first global bit line. The first sense amplifying device is configured to: in a leakage current detection mode, detect a leakage current of the selected memory cell block on a first global bit line to generate leakage current information; and in a data reading mode, provide a reference signal according to the leakage current information, and compare a readout signal on the first global bit line with the reference signal to generate readout data, wherein the leakage current detection mode happens before the data reading mode.

Abstract: A control method of a memory device is provided. When a target memory cell whose source is connected to a first source line needs to be read, a word line controller provides a first voltage to a word line corresponding to the target memory cell and also provides the first voltage to a word line corresponding to the next row of the target memory cell, so that the period when the word line corresponding to the target memory cell remains at the first voltage overlaps the period when the word line corresponding to the next row of the target memory cell remains at the first voltage. When the target memory cell needs to be read, a source line controller provides a second voltage to the first source line, and provides a third voltage to the second source line; the third voltage is not equal to the second voltage.

Abstract: A memory circuit and a memory programming method adapted to program flash memory are provided. The memory circuit includes a charge pumping circuit, a voltage regulator, a voltage sensor, and a plurality of switch circuits. The charge pumping circuit generates a pumping voltage and a pumping current. The voltage regulator is coupled to the charge pumping circuit and generates a programming voltage and a programming current to program the flash memory according to the pumping voltage and the pumping current. The voltage sensor is coupled to the voltage regulator to monitor a voltage value of the programming voltage. Each of the plurality of switch circuits includes a first terminal coupled to the voltage sensor and a second terminal coupled to the flash memory. A quantity of the plurality of switch circuits that are turned on is determined by the voltage value of the programming voltage.

Abstract: A memory circuit and a memory programming method adapted to program flash memory are provided. The memory circuit includes a charge pumping circuit, a voltage regulator, a voltage sensor, and a plurality of switch circuits. The charge pumping circuit generates a pumping voltage and a pumping current. The voltage regulator is coupled to the charge pumping circuit and generates a programming voltage and a programming current to program the flash memory according to the pumping voltage and the pumping current. The voltage sensor is coupled to the voltage regulator to monitor a voltage value of the programming voltage. Each of the plurality of switch circuits includes a first terminal coupled to the voltage sensor and a second terminal coupled to the flash memory. A quantity of the plurality of switch circuits that are turned on is determined by the voltage value of the programming voltage.

Abstract: This invention introduces an electronic apparatus and an operative method thereof which are capable of triggering an initialization operation for the electronic apparatus correctly. The electronic apparatus includes a plurality of latches and a power power-on-reset generator. The plurality of latches are coupled to memory cells and are configured to monitor memory data of the memory cells. The power-on-reset generator is coupled to the plurality of latches and is configured to generate a power-on-reset pulse to reset the electronic apparatus in response to a data corruption on at least one of the memory cells. The data corruption is detected during an initialization operation of the electronic apparatus according to memory data of the memory cells and corresponding hardwired code data.

Abstract: A control method for a memory is provided. In a test mode, a tendency check operation is performed for a cell array to define the tendency of the cell array. In a write mode: receiving external data; determining the tendency of the external data; comparing the tendency of the external data and the tendency of the cell array; inverting the external data and writing the inverted external data into the cell array in response to the tendency of the external data being different from the tendency of the cell array; and writing the external data into the cell array in response to the tendency of the external data being the same as the tendency of the cell array.

Abstract: A control method of a memory device is provided. When a target memory cell whose source is connected to a first source line needs to be read, a word line controller provides a first voltage to a word line corresponding to the target memory cell and also provides the first voltage to a word line corresponding to the next row of the target memory cell, so that the period when the word line corresponding to the target memory cell remains at the first voltage overlaps the period when the word line corresponding to the next row of the target memory cell remains at the first voltage. When the target memory cell needs to be read, a source line controller provides a second voltage to the first source line, and provides a third voltage to the second source line; the third voltage is not equal to the second voltage.

Abstract: A non-volatile memory and a data writing method are provided. The non-volatile memory includes a memory array and a memory controller. The memory array has a plurality of memory cells. The memory controller is configured to perform a data write operation on a plurality of selected memory cells. In the data write operation, the memory controller records a total number of times that a data write pulse is supplied, compares the total number of times of the data write pulse to a preset threshold value to obtain an indication value, and adjusts an absolute value of a voltage of the data write pulse according to the indication value.

Abstract: A memory apparatus and a data reading method thereof are provided. In the method, a plurality of memory cells of the memory apparatus are read to obtain read data, in which a threshold voltage of each memory cell is sensed and respectively compared with a first reference voltage and a second reference voltage to determine bit values. The first reference voltage and the second reference voltage are used to distinguish different states of the memory cell and the second reference voltage is larger than the first reference voltage. The bit values of the memory cells having the threshold voltage between the first reference voltage and the second reference voltage in the read data are gradually changed and syndromes of the changed read data are calculated. The read data is corrected according to values of the syndromes.

Abstract: A memory apparatus and a data reading method thereof are provided. In the method, a plurality of memory cells of the memory apparatus are read to obtain read data, in which a threshold voltage of each memory cell is sensed and respectively compared with a first reference voltage and a second reference voltage to determine bit values. The first reference voltage and the second reference voltage are used to distinguish different states of the memory cell and the second reference voltage is larger than the first reference voltage. The bit values of the memory cells having the threshold voltage between the first reference voltage and the second reference voltage in the read data are gradually changed and syndromes of the changed read data are calculated. The read data is corrected according to values of the syndromes.

Abstract: A memory device includes a memory array. The memory array has a plurality of memory cells arranged in rows and columns. The gates of the memory cells in the same row are coupled to each other and connected to a word line. The drains of the memory cells in the same column are coupled to each other and connected to a bit line. The sources of the memory cells in the same row are coupled to each other, and the sources of the memory cells in the two adjacent rows are connected to different respective source lines.

Abstract: A memory device and an operating method for controlling a non-volatile memory are provided. The non-volatile memory includes segments. Each of the segments includes memory cells. The operating method includes the following steps. A programming operation is performed multiple times on the memory cells in sequence according to increment commands, a segment order, and a memory cell order. When receiving a read command, a read operation is performed multiple times on the memory cells according to the segment order and the memory cell order until a last programmed memory cell is learned. According to an address of the last programmed memory cell, a replay-protected monotonic count value associated with a number of the increment commands is calculated.

Abstract: A non-volatile memory and a data writing method are provided. The non-volatile memory includes a memory array and a memory controller. The memory array has a plurality of memory cells. The memory controller is configured to perform a data write operation on a plurality of selected memory cells. In the data write operation, the memory controller records a total number of times that a data write pulse is supplied, compares the total number of times of the data write pulse to a preset threshold value to obtain an indication value, and adjusts an absolute value of a voltage of the data write pulse according to the indication value.

Abstract: A memory device includes a memory array. The memory array has a plurality of memory cells arranged in rows and columns. The gates of the memory cells in the same row are coupled to each other and connected to a word line. The drains of the memory cells in the same column are coupled to each other and connected to a bit line. The sources of the memory cells in the same row are coupled to each other, and the sources of the memory cells in the two adjacent rows are connected to different respective source lines.

Abstract: A control method for a memory is provided. In a test mode, a tendency check operation is performed for a cell array to define the tendency of the cell array. In a write mode: receiving external data; determining the tendency of the external data; comparing the tendency of the external data and the tendency of the cell array; inverting the external data and writing the inverted external data into the cell array in response to the tendency of the external data being different from the tendency of the cell array; and writing the external data into the cell array in response to the tendency of the external data being the same as the tendency of the cell array.

Abstract: A control method for a memory is provided. External data is received. An error correct code scheme is performed on the external data to generate first parity data. The number of logic values equal to a specific logic value in the external data and the first parity data is calculated to generate a calculation result. First reverse data is generated according to the calculation result and tendency data. The external data and the first parity data are inverted and the inverted external data, the inverted first parity data and the first reverse data are written into a cell array in response to the calculation result and the tendency data matching a predetermined condition. The external data, the first parity data and the first reverse data are written into the cell array in response to the calculation result and the tendency data not matching the predetermined condition.

Abstract: A memory circuit and a data bit status detector thereof are provided. The data bit status detector includes a sense amplifying circuit, a data receiving circuit, and a reference circuit. The sense amplifying circuit has a first sense input end and a second sense input end. The sense amplifying circuit senses and amplifies a difference between a first impedance on the first sense input end and a second impedance on the second sense input end to generate a sensing output signal. The data receiving circuit receives a plurality of bits of a data signal and provides the first impedance between the first sense input end and a reference grounding end according to the bits of the data signal. The reference circuit receives a plurality of bias voltages and provides the second impedance between the second sense input end and the reference grounding end according to the bias voltages.

Abstract: A flash memory storage apparatus and a reading method thereof are provided. The flash memory storage apparatus includes a memory cell array and a memory control circuit. The memory cell array includes at least one memory cell string coupled between a bit line and a source line. The memory control circuit is coupled to the memory cell array and configured to control a read operation of the memory cell array during the reading period. The reading period includes a pre-charge period and a discharge period. The source line performs a pre-charge operation on the bit line via a signal transmission path during the pre-charge period. The bit line performs a discharge operation on the source line via the same signal transmission path during the discharge period. The signal transmission path includes the memory cell string.