Abstract: A synchronous mirror delay (SMD) circuit is provided in the invention. The SMD circuit includes a delay monitor circuit (DMC), a forward delay circuit, a first shift circuit, a backward delay circuit, a second shift circuit and a clock-frequency-checker (CSC) circuit. The CSC circuit is coupled to the first shift circuit and the second shift circuit. The CSC circuit determines whether the frequency of the external input clock signal is slower than the frequency of the reference clock signal to generate a judgment result, and the CSC circuit transmits the judgment result to the first shift circuit and the second shift circuit. The first shift circuit and the second shift circuit determine whether to delay the external input clock signal according to the judgment result.

Abstract: A control method for a memory is provided. External data is received. An error correct code scheme is performed on the external data to generate first parity data. The number of logic values equal to a specific logic value in the external data and the first parity data is calculated to generate a calculation result. First reverse data is generated according to the calculation result and tendency data. The external data and the first parity data are inverted and the inverted external data, the inverted first parity data and the first reverse data are written into a cell array in response to the calculation result and the tendency data matching a predetermined condition. The external data, the first parity data and the first reverse data are written into the cell array in response to the calculation result and the tendency data not matching the predetermined condition.

Abstract: A memory circuit and a data bit status detector thereof are provided. The data bit status detector includes a sense amplifying circuit, a data receiving circuit, and a reference circuit. The sense amplifying circuit has a first sense input end and a second sense input end. The sense amplifying circuit senses and amplifies a difference between a first impedance on the first sense input end and a second impedance on the second sense input end to generate a sensing output signal. The data receiving circuit receives a plurality of bits of a data signal and provides the first impedance between the first sense input end and a reference grounding end according to the bits of the data signal. The reference circuit receives a plurality of bias voltages and provides the second impedance between the second sense input end and the reference grounding end according to the bias voltages.

Abstract: A random number generation system and a random number generation method thereof are provided. The random number generation system includes a random number generator, a random number selection circuit, and a random number logic circuit. The random number generator receives the random number request signal to provide a first random number sequence with n bits, where n is a positive integer. The random number selection circuit receives the random number request signal to provide a bit selection signal with n bits, wherein the bit selection signal is a time varying signal and is determined by the received random number request signal. The random number logic circuit receives the random number request signal, the first random number sequence and the bit selection signal, and in response to the random number request signal to adjust the first random number sequence using the bit selection signal to provide the second random number sequence.

Abstract: A synchronous mirror delay (SMD) circuit is provided in the invention. The SMD circuit includes a delay monitor circuit (DMC), a forward delay circuit, a first shift circuit, a backward delay circuit, a second shift circuit and a clock-frequency-checker (CSC) circuit. The CSC circuit is coupled to the first shift circuit and the second shift circuit. The CSC circuit determines whether the frequency of the external input clock signal is slower than the frequency of the reference clock signal to generate a judgment result, and the CSC circuit transmits the judgment result to the first shift circuit and the second shift circuit. The first shift circuit and the second shift circuit determine whether to delay the external input clock signal according to the judgment result.

Abstract: This invention introduces an electronic apparatus and an operative method thereof which are capable of triggering an initialization operation for the electronic apparatus correctly. The electronic apparatus includes a plurality of latches and a power power-on-reset generator. The plurality of latches are coupled to memory cells and are configured to monitor memory data of the memory cells. The power-on-reset generator is coupled to the plurality of latches and is configured to generate a power-on-reset pulse to reset the electronic apparatus in response to a data corruption on at least one of the memory cells. The data corruption is detected during an initialization operation of the electronic apparatus according to memory data of the memory cells and corresponding hardwired code data.

Abstract: A memory device and a programming method for a memory cell array are provided. The memory device includes a memory cell array, a selection switch, a row decoder, a voltage generator, and a memory controller. The memory controller controls the row decoder according to input data to adjust a control path sequence of address control signals, and the memory controller simultaneously controls the voltage generator to adjust a data path sequence of input data signals, so as to perform a programming operation on memory cells of the memory cell array.

Abstract: A memory storage apparatus including a plurality of word lines, a plurality of bit lines, a memory cell array, and a memory controller is provided. The memory cell array includes a plurality of memory cells. The memory cells are configured to store data. Each of the memory cells is coupled to the corresponding word line and the corresponding bit line. The memory controller is configured to perform a read operation to the memory cell array. The memory controller performs a pre-charge operation to part or all of the bit lines when the memory controller enables the word lines. In addition, an operating method of a memory storage apparatus is also provided.

Abstract: A column decoder of a memory device includes a first selection circuit, a second selection circuit and a decoding circuit. The first selection circuit and the second selection circuit are electrically connected in cascade with a memory array of the memory device. The decoding circuit receives a column address including a first sub-address and a second sub-address. The decoding circuit generates first decoded data and second decoded data for controlling the first selection circuit and the second selection circuit based on the first sub-address and the second sub-address. A first decoder in the decoding circuit decodes the first sub-address into the first decoded data, and the first decoded data is reversed in response to change of a first predetermined bit of the second sub-address.

Abstract: A random number generating system and a random number generating method thereof are provided. The random number generating system includes a random number generator, a random mask circuit, a bit reduction logic circuit and a receiver. The random number generator provides a random number sequence. The random mask circuit receives the random number sequence to provide a random number mask sequence and a random mask indication sequence, wherein bits of the random mask indication sequence in a first logical level corresponded to bits of the random number mask sequence in the high impedance state. The bit reduction logic circuit receives the random number sequence and the random mask indication sequence to provide the comparison key. The receiver receives a random number mask sequence to provide a verification key, where the verification key is the same as the comparison key.

Abstract: A random number generating system and a random number generating method thereof are provided. The random number generating system includes a random number generator, a random mask circuit, a bit reduction logic circuit and a receiver. The random number generator provides a random number sequence. The random mask circuit receives the random number sequence to provide a random number mask sequence and a random mask indication sequence, wherein bits of the random mask indication sequence in a first logical level corresponded to bits of the random number mask sequence in the high impedance state. The bit reduction logic circuit receives the random number sequence and the random mask indication sequence to provide the comparison key. The receiver receives a random number mask sequence to provide a verification key, where the verification key is the same as the comparison key.

Abstract: A random number generation system and a random number generation method thereof are provided. The random number generation system includes a random number generator, a random number selection circuit, and a random number logic circuit. The random number generator receives the random number request signal to provide a first random number sequence with n bits, where n is a positive integer. The random number selection circuit receives the random number request signal to provide a bit selection signal with n bits, wherein the bit selection signal is a time varying signal and is determined by the received random number request signal. The random number logic circuit receives the random number request signal, the first random number sequence and the bit selection signal, and in response to the random number request signal to adjust the first random number sequence using the bit selection signal to provide the second random number sequence.

Abstract: A flash memory storage apparatus and a reading method thereof are provided. The flash memory storage apparatus includes a memory cell array and a memory control circuit. The memory cell array includes at least one memory cell string coupled between a bit line and a source line. The memory control circuit is coupled to the memory cell array and configured to control a read operation of the memory cell array during the reading period. The reading period includes a pre-charge period and a discharge period. The source line performs a pre-charge operation on the bit line via a signal transmission path during the pre-charge period. The bit line performs a discharge operation on the source line via the same signal transmission path during the discharge period. The signal transmission path includes the memory cell string.

Abstract: A column decoder of a memory device includes a first selection circuit, a second selection circuit and a decoding circuit. The first selection circuit and the second selection circuit are electrically connected in cascade with a memory array of the memory device. The decoding circuit receives a column address including a first sub-address and a second sub-address. The decoding circuit generates first decoded data and second decoded data for controlling the first selection circuit and the second selection circuit based on the first sub-address and the second sub-address. A first decoder in the decoding circuit decodes the first sub-address into the first decoded data, and the first decoded data is reversed in response to change of a first predetermined bit of the second sub-address.

Abstract: A memory storage apparatus including a plurality of word lines, a plurality of bit lines, a memory cell array, and a memory controller is provided. The memory cell array includes a plurality of memory cells. The memory cells are configured to store data. Each of the memory cells is coupled to the corresponding word line and the corresponding bit line. The memory controller is configured to perform a read operation to the memory cell array. The memory controller performs a pre-charge operation to part or all of the bit lines when the memory controller enables the word lines. In addition, an operating method of a memory storage apparatus is also provided.

Abstract: A non-volatile semiconductor memory device capable of eliminating influence of bit line (BL) leakage on reading and a reading method thereof. The non-volatile semiconductor memory device includes a memory array, a semiconductor well having a plurality of erase units, and a source switch array having a plurality of source switches. Each of the source switches is coupled to a common source line of one erase unit of the semiconductor well. Only one source switch among the source switches coupled to a selected erase unit among the erase units of the semiconductor well for reading is enabled during a reading operation. Thus, the BL leakage is prevented from affecting the reading operation on memory cells of the memory array, thereby improving the reliability of the non-volatile semiconductor memory device.

Abstract: A method for operating a memory device is provided and includes the following steps. A first error correction code is generated according to user data. Then, the user data is written to the memory device. Moreover, the user data in the memory device is read, and a second error correction code is generated according to the read user data. Further, the first and the second error correction codes are written to the memory device.

Abstract: A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.

Abstract: A two transistor word line driver is disclosed. An example disclosed word line driver is simplified with common signals on the gates of the p-type and the n-type transistors. An example disclosed word line driver consumes less power by applying a negative voltage to a word line driver selected from multiple word line drivers.

Abstract: A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.