Patents by Inventor Wen-Chiao Ho
Wen-Chiao Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120300562Abstract: A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.Type: ApplicationFiled: August 1, 2012Publication date: November 29, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chun-Hsiung Hung, Wen-Chiao Ho, Kuen-Long Chang
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Patent number: 8270223Abstract: A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines. A first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source.Type: GrantFiled: December 1, 2009Date of Patent: September 18, 2012Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Shuo-Nan Hung, Chun-Hsiung Hung
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Patent number: 8259521Abstract: A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.Type: GrantFiled: August 13, 2008Date of Patent: September 4, 2012Assignee: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Wen-Chiao Ho, Kuen-Long Chang
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Publication number: 20120210193Abstract: A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.Type: ApplicationFiled: April 26, 2012Publication date: August 16, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wen-Chiao HO, Chin-Hung CHANG, Chun-Hsung HUNG, Kuen-Long CHANG
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Patent number: 8223559Abstract: A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an nth phase are programmed into the targeted multi-level cells. Data corresponding to an (n+1)th phase is modified to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass a programming verification process according to an nth programming verification voltage. The above steps are repeated until n is equal to a maximum, n being a positive integer.Type: GrantFiled: December 16, 2010Date of Patent: July 17, 2012Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Kuen-Long Chang, Chun-Hsiung Hung
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Patent number: 8208332Abstract: A compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal, and a second terminal for receiving a reference voltage. The emulation circuit is coupled to the first terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot.Type: GrantFiled: August 27, 2010Date of Patent: June 26, 2012Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Ji-Yu Hung, Chun-Hsiung Hung, Shuo-Nan Hung
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Patent number: 8190984Abstract: A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.Type: GrantFiled: March 23, 2011Date of Patent: May 29, 2012Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Chun-Hsiung Hung, Kuen-Long Chang
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Patent number: 8176373Abstract: A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block.Type: GrantFiled: March 8, 2011Date of Patent: May 8, 2012Assignee: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Wen-Chiao Ho
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Publication number: 20110173512Abstract: A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.Type: ApplicationFiled: March 23, 2011Publication date: July 14, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wen-Chiao HO, Ching-Hung Chang, Chung-Hsiung Hung, Kuen-Long Chang
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Patent number: 7975111Abstract: A memory and a method applied in one program command for the memory are provided. The memory includes a buffer and at least one program unit. The method includes the following steps. First, enter the program command to the memory. Next, enter user data to the buffer. Read the data of the program unit. Determine whether the user data fill the buffer. Fill the part of the buffer unoccupied by the user data with the data of the program unit if the user data do not fill the buffer. Erase the program unit if the program unit is not empty. Finally, program the data of the buffer into the program unit.Type: GrantFiled: November 13, 2008Date of Patent: July 5, 2011Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Hsiung Hung, Wen-Chiao Ho
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Publication number: 20110161750Abstract: A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block.Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chun-Hsiung Hung, Wen-Chiao Ho
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Publication number: 20110149675Abstract: A two transistor word line driver is disclosed. An example disclosed word line driver is simplified with common signals on the gates of the p-type and the n-type transistors. An example disclosed word line driver consumes less power by applying a negative voltage to a word line driver selected from multiple word line drivers.Type: ApplicationFiled: May 21, 2010Publication date: June 23, 2011Applicant: Macronix International Co., Ltd.Inventors: Chin-Hung Chang, Wen-Chiao Ho, Chun-Hsiung Hung
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Patent number: 7965551Abstract: A method for metal bit line arrangement is applied to a virtual ground array memory having memory cell blocks. Each memory cell block has memory cells and m metal bit lines, wherein m is a positive integer. The method includes the following steps. First, one of the memory cells is selected as a target memory cell. When the target memory cell is being read, the metal bit line electrically connected to a drain of the target memory cell is a drain metal bit line, and the metal bit line electrically connected to a source is a source metal bit line. Next, a classification of whether the other metal bit lines are charged up when the target memory cell is being read is made. Thereafter, the m metal bit lines are arranged such that charged up metal bit lines are not adjacent to the source metal bit line.Type: GrantFiled: February 7, 2007Date of Patent: June 21, 2011Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Kuen-Long Chang, Chun-Hsiung Hung
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Publication number: 20110128786Abstract: A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines, wherein a first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source.Type: ApplicationFiled: December 1, 2009Publication date: June 2, 2011Inventors: Wen-Chiao Ho, Chin-Hung Chang, Shuo-Nan Hung, Chun-Hsiung Hung
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Publication number: 20110085380Abstract: A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an nth phase are programmed into the targeted multi-level cells. Data corresponding to an (n+1)th phase is modified to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass a programming verification process according to an nth programming verification voltage. The above steps are repeated until n is equal to a maximum, n being a positive integer.Type: ApplicationFiled: December 16, 2010Publication date: April 14, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Kuen-Long Chang, Chun-Hsiung Hung
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Patent number: 7925939Abstract: A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block.Type: GrantFiled: September 26, 2008Date of Patent: April 12, 2011Assignee: Macronix International Co., LtdInventors: Chun-Hsiung Hung, Wen-Chiao Ho
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Patent number: 7925960Abstract: A method for checking reading errors of a memory includes receiving a first data fragment and accordingly generating a first ECC and a first count index; writing the first data fragment, the first ECC and the first count index into a memory; reading the first data fragment from the memory as a second data fragment, generating a second ECC and second count index according to the second data fragment; determining whether the first count index and second count index are equal; determining whether the first ECC and the second ECC are equal; and outputting the second data fragment when the first count index is equal to the second count index and the first ECC is equal to the second ECC.Type: GrantFiled: March 26, 2007Date of Patent: April 12, 2011Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Chun-Hsiung Hung, Kuen-Long Chang
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Patent number: 7889572Abstract: A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory cell. The reading control circuit is for selectively applying a working voltage to the source line.Type: GrantFiled: September 4, 2008Date of Patent: February 15, 2011Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Kuen-Long Chang, Chun-Hsiung Hung
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Patent number: 7885120Abstract: A method for double programming of multi-level-cell (MLC) programming in a multi-bit-cell (MBC) of a charge trapping memory that includes a plurality of charge trapping memory cells is provided. The double programming method is conducted in two phrases, a pre-program phase and a post-program phase, and applied to a word line (a segment in a word line, a page in a word line, a program unit or a memory unit) of the charge trapping memory. A program unit can be defined by input data in a wide variety of ranges. For example, a program unit can be defined as a portion (such as a page, a group, or a segment) in one word line in which each group is selected for pre-program and pre-program-verify, either sequentially or in parallel with other groups in the same word line.Type: GrantFiled: May 13, 2009Date of Patent: February 8, 2011Assignee: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Wen-Chiao Ho, Kuen-Long Chang
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Patent number: 7869276Abstract: A memory includes many memory regions. The memory regions have multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The first bit line is coupled to a first column of the multi-level cells. The second bit line is coupled to a second column of the multi-level cells. The data buffer is coupled to the first bit line and the second bit line and for storing data to be programmed into the multi-level cells. The protecting unit is coupled to the first bit line, the second bit line and the data buffer and is for preventing a programming error from occurring.Type: GrantFiled: November 29, 2007Date of Patent: January 11, 2011Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Kuen-Long Chang, Chun-Hsiung Hung