Patents by Inventor Wen Chou

Wen Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5419038
    Abstract: A three dimensional thin-film interconnector is fabricated by depositing a dielectric layer onto the surface of a substrate, depositing a layer of conductive material onto the dielectric layer to form a signal plane, depositing a dielectric layer onto the surface of the signal plane, forming a plurality of through holes in the dielectric layer that extend to the signal plane, and filling the through holes with an electrically conductive material to form vias. The sequence of forming a signal plane, depositing a dielectric layer, forming a plurality of through holes, and filling the through holes is repeated until a predetermined number of signal planes and a predetermined arrangement of vias are obtained. The through holes are formed at locations in the dielectric layers corresponding to both predetermined electrical connections and the vias in a preceding dielectric layer. The signal planes are formed at different locations on the substrate.
    Type: Grant
    Filed: June 17, 1993
    Date of Patent: May 30, 1995
    Assignee: Fujitsu Limited
    Inventors: Wen-chou V. Wang, Solomon I. Beilin, William T. Chou, David Kudzuma, Michael G. Lee, Michael G. Peters, James J. Roman, Som S. Swamy
  • Patent number: 5406446
    Abstract: A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed and a bottom contact metalization layer is applied to the surface of the bottom contact layers. A portion of the metalization layer is removed and an insulating layer is formed on the surface of the bottom contact metalization layer. A ground metalization feedthrough and a power metalization feedthrough are formed at the surface of the insulating layer. A sequence of top contact layers are applied to the surface of the insulating layer and a front side ground terminal and front side power terminal are formed.
    Type: Grant
    Filed: February 25, 1994
    Date of Patent: April 11, 1995
    Assignee: Fujitsu Limited
    Inventors: Michael G. Peters, William T. Chou, Wen-chou V. Wang, Michael G. Lee, Solomon I. Beilin
  • Patent number: 5404265
    Abstract: A bypass capacitor for use with an integrated circuit module, and method of making the same, are shown. The integrated circuit module comprises an integrated circuit "chip" mounted in opposing relationship to a carrier substrate and having a plurality of interconnects, such as solder bumps or wire interconnects, for providing signal lines and supplying power to the chip. Some of the interconnects are, instead, used to form capacitors such that bypass capitance is placed in close proximity to the chip, while not using up valuable real estate on the chip or on the carrier substrate. Various embodiments of such bypass capacitors are shown.
    Type: Grant
    Filed: August 28, 1992
    Date of Patent: April 4, 1995
    Assignee: Fujitsu Limited
    Inventors: Larry L. Moresco, David G. Love, Wen-Chou V. Wang
  • Patent number: 5382827
    Abstract: A semiconductor chip carrier has a first substrate and at least one second substrate. The first substrate is for carrying at least one semiconductor chip of integrated circuits. The first substrate has predetermined functional elements for connection to the integrated circuits of the at least one semiconductor chip. Such a second substrate is directly coupled to the first substrate. The second substrate is capable of being independently created and has predetermined electrical functional elements for connection to the integrated circuits of the semiconductor chip. The electrical functional elements of each second substrate are of one type and are different than the electrical functional elements of the other second substrates and the first substrate.
    Type: Grant
    Filed: August 7, 1992
    Date of Patent: January 17, 1995
    Assignee: Fujitsu Limited
    Inventors: Wen-chou V. Wang, William T. Chou
  • Patent number: 5376586
    Abstract: A method of curing an organic dielectric layer, such as polyimide, used in a multichip module is disclosed. The method comprises heating the uncured polyimide layer to a temperature above its glass transition temperature, and irradiating the layer with a uniform flux of electrons, as in an e-beam apparatus. The process reduces deterioration at the interface between the dielectric films and the metal layers which when high temperature thermal curing is utilized, and reduces the stress of the resulting film. Multiple dielectric layers can be applied in this manner.
    Type: Grant
    Filed: May 19, 1993
    Date of Patent: December 27, 1994
    Assignee: Fujitsu Limited
    Inventors: Solomon I. Beilin, Wen-chou V. Wang, William T. Chou
  • Patent number: 5333385
    Abstract: A movable and automatic sawing and clamping device for wood, wherein two pipe-like frame portions are separated from each other by a suitable distance. Two sets of horizontal pieces are orthogonal to these portions and are separately provided therebetween. A clamping device can be formed between these horizontal pieces for clamping a saw tool therebetween. The whole clamping framework can be moved by means of a plurality of bottom rollers to cut the workpiece.
    Type: Grant
    Filed: April 27, 1993
    Date of Patent: August 2, 1994
    Inventor: Chen-Wen Chou
  • Patent number: 5323520
    Abstract: A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed and a bottom contact metalization layer is applied to the surface of the bottom contact layers. A portion of the metalization layer is removed and an insulating layer is formed on the surface of the bottom contact metalization layer. A ground metalization feedthrough and a power metalization feedthrough are formed at the surface of the insulating layer. A sequence of top contact layers are applied to the surface of the insulating layer and a front side ground terminal and front side power terminal are formed.
    Type: Grant
    Filed: April 29, 1993
    Date of Patent: June 28, 1994
    Assignee: Fujitsu Limited
    Inventors: Michael G. Peters, William T. Chou, Wen-chou V. Wang, Michael G. Lee, Solomon I. Beilin