Abstract: A method of fabricating a multi-layer interconnected substrate structure. The inventive method includes forming a multi-layer structure from multiple, pre-fabricated power and/or signal substrates which are laminated together. A drill is then used to form a via through the surface of a ring-type pad down to a desired depth in the multi-layer structure. The via hole is cleaned and then filled with a conductive material. The via so formed between two or more substrates is self-aligned by using the ring pad(s). This contributes to an increased signal routing density compared to conventional methods.

Abstract: An improved keyboard structure comprises a base, a pan body, and a top cover. A user is supposed to turn a turnable functional pushbutton to a specified function item, then click the pan body for the computer to execute the related program.

Abstract: A method is described for manufacturing a shallow trench isolation. The method comprises the steps of providing a substrate having a pad oxide layer, a mask layer and a trench, wherein the trench penetrates through the mask layer and the pad oxide layer and into the substrate. A liner oxide layer is formed on a portion of the sidewall of the trench in the substrate. A silicon layer is formed in the trench with a same surface level as the interface between the substrate and the pad oxide layer and an insulating layer is formed on the silicon layer.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is provided. The method has steps of sequentially forming an oxide layer, a polysilicon layer and a cap layer on a semiconductor substrate to form a first-stage gate. An interchangeable source/drain region with a lightly doped drain (LDD) structure is formed in the substrate at each side of the first-stage gate. An insulating layer is formed over the substrate, and is planarized so as to exposed the cap layer. Removing the exposed cap layer forms an opening that exposes the polysilicon layer. Using the insulating layer as a mask, a self-aligned selective local implantation process is performed to form a threshold-voltage doped region and an anti-punch-through doped region below the oxide layer in the substrate. A conductive layer is formed over the substrate to fill the opening.

Abstract: A method for forming an amorphous silicon layer over the terminals of a MOS transistor. The method includes the steps of forming a mask layer having an opening that exposes the gate polysilicon layer over the MOS transistor. Next, using the mask layer as a mask, an inactive ion implant operation is carried out such that inactive ions are implanted into the gate polysilicon layer. Thereafter, again using the mask layer as a mask, a first heavy bombarding operation is carried out, implanting ions locally. Finally, the mask layer is removed and then a second heavy bombarding operation is carried out, implanting ions globally.

Abstract: A method of fabricating a metal oxide semiconductor includes formation of a gate on a substrate. A source/drain extension is formed beside the gate in the substrate. An ion implantation step is performed to implant heavy impurities with a low diffusion coefficient in the substrate. A heavily doped halo region is formed in the substrate below the source/drain extension. A tilt-angled halo implantation step is performed to form a halo-implanted region in the substrate to the side of the source/drain extension below the gate.

Abstract: The channel doping profile of a PMOS field effect transistor consists of a shallow distribution of a P-type dopant as a threshold adjust implant, a deeper distribution of an N-type dopant as an buried channel stop implant and a still deeper implantation of an N-type dopant as an antipunchthrough implant. A junction is formed between the P-type threshold adjust implant and the N-type buried channel stop implant at a relatively shallow depth so that the depth of the buried channel region is limited by the buried channel stop implant, reducing the short channel effect. The channel doping profile is formed so that diffsion of impurities from the channel region to the gate oxide is prevented. The buried channel stop implant is made first through a sacrificial oxide layer. The sacrificial oxide is etched and a gate oxide layer and a thin film of polysilicon are deposited on the surface of the gate oxide.

Abstract: An encapsulation process for flip-chip bonding chips to a substrate encapsulates solder balls on the chip in a separate encapsulation process in which the chip is coated with encapsulation layer and then a portion of the encapsulation layer is removed to expose a portion of the solder balls.

Abstract: A flexible membrane circuit structure for keyboard comprises a substrate; a membrane circuit structure arranged on the substrate and comprising an upper membrane layer and a lower circuit layer, a plurality of movable keytops depressibly arranged on the substrate and each corresponding to one the conductive contact; at least one fixed keytop arranged on marginal location of the keyboard and being not depressible. Each membrane circuit layer has conductive contacts. The conductive contacts on the upper membrane layer has a predetermined separation with corresponding conductive contacts on the lower membrane layer. The upper membrane layer and the lower circuit layer is bridged by at least one folded plate such that the upper membrane layer electrically and mechanically connected with the lower circuit layer. The folded plate received within the fixed keytop to prevent the breaking of the folded plates.

Abstract: A new improvement for selective epitaxial growth is disclosed. In one embodiment, the present invention provides a low power metal oxide semiconductor field effect transistor (MOSFET), which includes a substrate. Next, a gate oxide layer is formed on the substrate. Moreover, a polysilicon layer is deposited on the gate oxide layer. Patterning to etch the polysilicon layer and the gate oxide layer to define a gate. First ions are implanted into the substrate by using said gate as a hard mask. Sequentially, a liner oxide is covered over the entire exposed surface of the resulting structure. Moreover, a conformal first dielectric layer and second dielectric layer are deposited above the liner oxide in proper order. The second dielectric layer is etched back to form a dielectric spacer on sidewall of the first dielectric layer.

Abstract: An improved positioning structure of pushbutton in keyboard (2) comprises a base, a printed circuit board (PCB) attached on the base having a plurality of pivot-jointing portions protrusively disposed on its surface for defining a plurality of enclosed assembly-jointing sections, a link (bridge) disposed at the assembly-jointing section having a movable shaft axially jointed with the pivot-jointing portion, an elastomer arranged on the link, and a key cap disposed on the elastomer being coupled with a positioning shaft at one end of the link. By assembling the abovesaid components, a waterproof and thinner keyboard at lower cost is realizable.

Abstract: A method for cleaning a silicon wafer. The method includes intentionally exposing the wafer into a volatile solvent with a polarity between about 2 and 4, whereby the wafer is cleaned by the solvent such that the formation of silicon recesses in source/drain extension regions on the silicon wafer can be prevented or avoided.

Abstract: A coupling mechanism interconnects a rotatable connecting end of a support on a broaching machine and a bit holder which includes a rotary hollow shaft and a mandrel received in the hollow shaft. The coupling mechanism includes a first coupling member that has a first disk part and a first neck part, and a second coupling member that has a second disk part and a second neck part. The first neck part is connected to the connecting end of the support. The first disk part has a plurality of posts projecting axially from the first disk part opposite to the first neck part. The second neck part extends into the hollow shaft for connection with the mandrel. The second disk part has slide holes which extend axially in the second disk part at locations radially outward of the second neck part so as to receive the posts. The second coupling member is guided by the posts and the slide holes for sliding axially relative to the first coupling member.

Abstract: A semiconductor read-only memory (ROM) device is provided and includes an array of diode-based memory cells for storing binary data. Whether a memory cell of the ROM device is set to a permanently-ON or OFF state, depends upon whether the memory cell is formed with a junction diode, wherein the presence of a junction diode in the memory cell causes the memory cell to be set to a permanently-ON state. Formation of the junction diode includes the step of forming a plurality of parallel-spaced first diffusion regions of a semiconductor type, to serve as a plurality of bit lines. An insulating layer is then formed to cover the first diffusion regions. A plurality of contact windows are formed at predefined locations of the insulating layer where a first group of memory cells, set to a permanently-ON state, are formed. The unexposed portions of the first diffusion regions are associated with a second group of memory cells that are set to a permanently-OFF state.

Abstract: An improved bearing mechanism with both a relative larger axial force adjustment mechanism and a relatively smaller axial force adjustment mechanism, works in conjunction with the control rod of a vertical blind system or a roller shade system to provide superior bearing and load handling capability. A primary adjustment mechanism provides a first magnitude range of urging force of a bearing structure toward a housing as by the use of an axial bolt or the like. Inasmuch as this is difficult to adjust without removal of the roller shade and such adjustment is difficult gauge physically, a secondary adjustment structure enables tension adjustment over a second magnitude range of urging force and which is accessible without having to remove the roller. The secondary adjustment structure is a wedge which operates adjacent the main tension member.

Abstract: A structure of a spacer in a semiconductor device is disclosed. Firstly, a gate without a spacer is provided on a substrate. A first insulating layer is formed on the sidewall of the gate. After a lightly doped drain is subsequently achieved in the substrate, a second insulating layer is formed on the first spacer. The process following this embodiment described above is to form a heavily doped drain in the substrate, then the whole MOSFET fabrication is completed. The present invention can enhance the stability of resistance of the gate and reduce pollution of the machine. Therefore, quality and efficiency of the fabrication of MOSFET will be enhanced.

Abstract: An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed through rigid segments and signals are routed through a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected.