Abstract: Described are methods of manufacturing large substrate capacitors for multi-chip module applications and the like using procedures compatible with common semiconductor fabrication procedures. A capacitor is formed where the top electrode thereof is divided into a plurality of segmented pads which are initially electrically isolated from one another. Each segmented pad forms a capacitor with the underlying dielectric layer and bottom capacitor electrode. Each segmented capacitor is electrically tested, and defective ones are identified. A conductive layer is thereafter formed over the segmented pads such that the conductive layer is electrically isolated from the pads of defective capacitors. The conductive layer electrically couples the good capacitors in parallel to form a high-value bypass capacitor which has low parasitic inductance. Large embedded MCM bypass capacitors can thereby be fabricated with minimal impact to the overall manufacturing yield.

Abstract: Methods of forming patterns in photo-sensitive resist layers with high aspect ratio features are described. The photosensitive layer is patterned exposed to actinic radiation and thereafter developed. For high aspect ratio patterns, the inventors have often observed a residue of resist material at the bottom of such features, and that this residue interferes with subsequent processing, such as filling the pattern with metal by a plating operation. To remove this residue, the patterned locations of the resist are exposed to a low dose of low-energy electron beam radiation, preferably having energy of less than 6 KeV and dosage of less than 200 .mu.C/cm.sup.2. After the electron beam exposure, the aperture is again exposed to a developer solution, which may be of the same composition as the developer initially used to develop the patterns.

Abstract: A method of forming MOS components provides that after the formation of the gate and the doped source/drain regions, a polysilicon layer is deposited and planarized using a chemical-mechanical polishing method. The resulting unremoved polysilicon layer acts as source/drain terminals. Through these arrangements, the ion doped source/drain regions will have shallow junctions, yet their junction integrity will not be compromised by subsequent contact window etching and metallization processes. Furthermore, the front-end processes for forming the MOS component provide a good planar surface that offers great convenience for the performance of subsequent back-end processes.

Abstract: A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.

Abstract: The present invention relates to a method of forming lightly doped drains in metallic oxide semiconductor (MOS) components. The method includes forming a first, second, and third insulating layer above a silicon substrate having a gate, etching back the layers to leave behind L-shaped first spacers on sidewalls of the gate, followed by doping second type ions into the silicon substrate to form first lightly doped drains in the silicon substrate surface below the L-shaped first spacers, and second lightly doped drains in the silicon substrate surface elsewhere, further forming a fourth insulating to form third spacers, and using the using the third spacers, the first insulating layer, and the gate as masks when doping second type ions into the silicon substrate so as to form source/drain regions in silicon substrate surfaces not covered by the third spacers. Such a method produces greater yield and reduces leakage current from the transistor components.

Abstract: Methods of forming high-aspect ratio blind apertures and thereafter filling the apertures with a plating solution are disclosed. A layer of photosensitive material is pattern exposed to actinic radiation to define the apertures, and thereafter exposed to aqueous developer solution. The apertures are then rinsed with water and thereafter exposed to plating solution without drying the aperture of water or developer solution. This is contrary to conventional practice where photoresist layers are dried, and usually post-baked after the development step in order to improve dimensional integrity and reduce swelling of the photoresist material.

Abstract: An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.

Abstract: Methods for pretreating patterned masks layers, such as photoresist masks, with electron-beam radiation for use in high temperature processes are disclosed. The electron-beam exposure deactivates compounds within the mask material which would ordinarily decompose and produce gasses within the photoresist layer. The gasses cause blistering in the untreated photoresist layer, which in turn degrades the dimensional integrity of the untreated layer.

Abstract: A three dimensional module for housing a plurality of integrated circuit chips is shown. The IC chips are mounted in rows on a plurality of substrates. Parallel to each row are communications bars which provide signal paths allowing chips on one substrate to communicate with those on another substrate. The communications bars also serve as spacers between substrates, thereby forming cooling channels. The IC chips are disposed in the cooling channels so that they come into direct contact with the cooling fluid. Signal lines to and from the IC chips are kept as separated as possible from the power lines so as to minimize noise. To this end, relatively thick power supply straps are mounted to each substrate below each row of IC chips. The power supply straps are, in turn, connected to power feed straps such that a very low impedance power supply path to the IC chips is maintained.

Abstract: Simple and cost-effective methods for forming tall, high-aspect ratio structures in a material layer comprising a first layer of a image-reversal-type photo-sensitive material and a second layer of a positive-type photo-sensitive material is disclosed. The layers are formed, exposed to actinic radiation, and developed such that the formation, exposure, and development of the second layer does not substantially modify or destroy the patterns formed in the first layer. In one embodiment, the first layer is exposed to actinic radiation through a first mask comprising the complimentary image, or negative, of a desired high-aspect ratio structure. The image in the first layer is then reversed by heating to an elevated temperature and subsequently blank flood exposure of actinic radiation. A second layer of a positive type photo-sensitive material chemically compatible with the IRP layer is then formed over the first layer.

Abstract: A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed in the bottom contact layer and is electrically isolated from remaining portions of the bottom contact layers by insulating plugs. A bottom contact metalization layer is applied to the surface of the bottom contact layers and the insulating plugs. A dielectric layer is formed on the surface of the bottom contact metalization layer. A ground metalization via and a power metalization via are formed at the surface of the dielectric layer.

Abstract: The improved system utilizes a track which has a bowed internal surface to prevent the wheel of the carrier from frictional engagement with the side of the track. The curved surface which faces the wheels will not be engaged by the wheels even where the carrier turns to one side or the other. This is accomplished while leaving the innermost portions of the raceway in the same width position with regard to the wheels as is usual to prevent the carrier from coming off-track. The tolerances for the inner corners of the raceway opposing the wheels may be reduced to further prevent the possibility of jamming in the track.

Abstract: A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.

Abstract: A compact, reliable, and efficient cooling system for semiconductor chips is disclosed. In one embodiment, a plurality of semiconductor chips have their active surfaces mounted to a major substrate which provides electrical connections among the chips, and a cooling channel is formed above the major substrate and each chip for conducting a cooling fluid over the back surface of the chips. To increase cooling efficiency, heat sink arrays are formed on the back surfaces of the chips, each array including a plurality of heat conducting elements attached to the back surface. The arrays may be readily and inexpensively constructed with photo-lithography or wire bonding techniques. To control the flow of cooling fluid around the chip edges and to prevent cavitation of the cooling fluid a cavitation and flow control plate disposed at the bottom surface of the cooling channel and formed around the edges of the chips is included.

Abstract: A semiconductor device is manufactured by subdividing the chip carrier into a plurality of functional substrates, such as a signal connection substrate, a capacitor substrate, a resistor substrate and a power supply substrate. The several substrates are individually manufactured and tested before they are assembled. Advantageously, the manufacturing and testing of the substrates are carried out in parallel, so as to reduce manufacturing time of the semiconductor device.Each substrate has a top interconnect layer and a bottom interconnect layer. Each interconnect layer has a plurality of bond pads in an identical pattern. The pads are formed using the same design rules, structure, pitch, diameter and fabrication process for each layer. This identity allows the different functional substrates to be electrically interchanged without changing the interconnection layers. Although changes internal in the substrate may be required.

Abstract: Interconnect carriers for coupling integrated circuit chips to major substrates and methods for making the same are disclosed. The interconnect carrier comprises a relatively thin resilient supporting layer, a plurality of electrically conductive vias formed through the surfaces of the supporting layer, and an outer frame disposed around the periphery of the supporting layer. The supporting layer preferably comprises an electrically insulating material. The flexibility of the supporting layer enables the layer to more readily conform to the warpages of the IC chip and supporting substrate, while the outer frame provides mechanical support and prevents the supporting layer from folding, twisting, and/or stretching. The thickness of the supporting layer may be substantially reduced over that of prior art interposers to enable methods for constructing smaller diameter vias.

Abstract: A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed in the bottom contact layer and is electrically isolated from remaining portions of the bottom contact layers by insulating plugs. A bottom contact metalization layer is applied to the surface of the bottom contact layers and the insulating plugs. A dielectric layer is formed on the surface of the bottom contact metalization layer. A ground metalization via and a power metalization via are formed at the surface of the dielectric layer.

Abstract: A high density through-hole interconnect with high aspect ratio vias is formed by sequentially forming layers of dielectric material on a previous dielectric layer. After each layer is formed, a plurality of through holes are etched through each layer and filled or metalized with an electrically conductive material having a coefficient of thermal expansion matching that of the dielectric layers and the integrated circuit that it will connect with. Preferably, the process of forming dielectric layers, forming through holes, and metalizing the through holes is repeated until the metalized through holes have an aspect ratio in the range of from 6 to 10. A support structure is constructed to interconnect with and support the metalized vias while the dielectric material is removed. A second dielectric material having the desired mechanical and electrical properties is poured into the support structure to fill the space between the metalized vias and allowed to solidify.

Abstract: The present invention provides an improved structure for compact disk cases comprising a hollow rectangular case body having a fully open top portion, a disk holder placed in the case body, and a cover plate covering the case body, the left and right sidewalls of the case body being each provided at the lower section with a groove extending from the front to the rear, and the bottom ends of the left and right sidewalls of the cover plate being each formed inwardly with an integral guide rail for the cover plate to slip-fit with the case body such that when both are closed together, the stop strip on the front side of the cover plate snaps into the arcuate ducts in the front end of the disk holder, and in use, by properly applying force, the cover plate will be slid backward to position, thus resulting in smooth and positive sliding to open and close for the structure as a whole.

Abstract: A three dimensional module for housing a plurality of integrated circuit chips is shown. The IC chips are mounted in rows on a plurality of substrates. Parallel to each row are communications bars which provide signal paths allowing chips on one substrate to communicate with those on another substrate. The communications bars also serve as spacers between substrates, thereby forming cooling channels. The IC chips are disposed in the cooling channels so that they come into direct contact with the cooling fluid. Signal lines to and from the IC chips are kept as separated as possible from the power lines so as to minimize noise. To this end, relatively thick power supply straps are mounted to each substrate below each row of IC chips. The power supply straps are, in turn, connected to power feed straps such that a very low impedance power supply path to the IC chips is maintained.