Patents by Inventor Wen-Chuan Tai
Wen-Chuan Tai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240044889Abstract: A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; and a cap structure attached to the buried oxide layer, the cap structure comprising a microneedle.Type: ApplicationFiled: August 10, 2023Publication date: February 8, 2024Inventors: Allen Timothy Chang, Jui-Cheng Huang, Wen-Chuan Tai, Yu-Jie Huang
-
Publication number: 20240038597Abstract: A method and a system for detecting a semiconductor device are provided. The method comprises obtaining an image of the semiconductor device, evaluating a feature of the image, detecting a defect of the semiconductor device based on the feature, extracting a defect information for the defect, calculating a defect die ratio (DDR) in response to the defect and analyzing a relation between the DDR and the defect information.Type: ApplicationFiled: July 28, 2022Publication date: February 1, 2024Inventors: FAN HU, WEN-CHUAN TAI, HSIANG-FU CHEN, I-CHIEH HUANG, TZU-CHIEH WEI, KANG-YI LIEN
-
Publication number: 20230399226Abstract: The present disclosure relates to an integrated chip including a semiconductor device substrate and a plurality of semiconductor devices arranged along the semiconductor device substrate. A micro-electromechanical system (MEMS) layer overlies the semiconductor device substrate. The MEMS layer includes a first moveable mass and a second moveable mass. A capping layer overlies the MEMS layer. The capping layer has a first lower surface directly over the first moveable mass and a second lower surface directly over the second moveable mass. An outgas layer is on the first lower surface and directly between the first pair of sidewalls. A lower surface of the outgas layer delimits a first cavity in which the first moveable mass is arranged. The second lower surface of the capping layer delimits a second cavity in which the second moveable mass is arranged.Type: ApplicationFiled: June 8, 2022Publication date: December 14, 2023Inventors: Fan Hu, Wen-Chuan Tai, Li-Chun Peng, Hsiang-Fu Chen, Ching-Kai Shen, Hung-Wei Liang, Jung-Kuo Tu
-
Publication number: 20230393091Abstract: A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; a carrier substrate on the MLI structure; a first through substrate via (TSV) structure extending though the carrier substrate and configured to provide an electrical connection between the MLI structure and a separate die; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; and a microfluidic channel cap structure attached to the buried oxide layer.Type: ApplicationFiled: August 17, 2023Publication date: December 7, 2023Inventors: Allen Timothy Chang, Jui-Cheng Huang, Wen-Chuan Tai, Yu-Jie Huang
-
Patent number: 11834325Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure.Type: GrantFiled: June 15, 2022Date of Patent: December 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fan Hu, Chun-Ren Cheng, Hsiang-Fu Chen, Wen-Chuan Tai
-
Publication number: 20230382724Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Inventors: Wen-Chuan Tai, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu, Fan Hu
-
Publication number: 20230381815Abstract: A method of forming a transducer includes depositing a first dielectric layer on a first electrode, patterning the first dielectric layer to form first protrusions and second protrusions, where a first diameter of each of the first protrusions is larger than a second diameter of each of the second protrusions; and bonding the first dielectric layer to a second electrode using a second dielectric layer, where sidewalls of the second dielectric layer define a cavity disposed between the first electrode and the second electrode, and where the first protrusions are disposed in the cavity.Type: ApplicationFiled: May 24, 2022Publication date: November 30, 2023Inventors: Chi-Yuan Shih, Shih-Fen Huang, Yan-Jie Liao, Wen-Chuan Tai
-
Publication number: 20230373780Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity.Type: ApplicationFiled: August 7, 2023Publication date: November 23, 2023Inventors: Fan Hu, Chun-Ren Cheng, Hsiang-Fu Chen, Wen-Chuan Tai
-
Publication number: 20230331546Abstract: A MEMS package is provided. The MEMS package includes a metallization layer, a planarization structure, a MEMS device structure, a cap structure and a pressure adjustment element. The planarization structure has an inner sidewall defining a first cavity exposing the metallization layer. The MEMS device structure is bonded to the planarization structure. The MEMS device structure includes a movable element over the first cavity. The cap structure is bonded to the MEMS device structure and has an inner sidewall defining a second cavity facing the movable element. The pressure adjustment element is disposed in the second cavity.Type: ApplicationFiled: April 19, 2022Publication date: October 19, 2023Inventors: FAN HU, WEN-CHUAN TAI, LI-CHUN PENG, HSIANG-FU CHEN
-
Publication number: 20230299028Abstract: A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.Type: ApplicationFiled: March 15, 2022Publication date: September 21, 2023Inventors: WEN-CHUAN TAI, FAN HU, HSIANG-FU CHEN, LI-CHUN PENG
-
Patent number: 11747298Abstract: A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; a carrier substrate on the MLI structure; a first through substrate via (TSV) structure extending though the carrier substrate and configured to provide an electrical connection between the MLI structure and a separate die; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; and a microfluidic channel cap structure attached to the buried oxide layer.Type: GrantFiled: November 11, 2020Date of Patent: September 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Allen Timothy Chang, Jui-Cheng Huang, Wen-Chuan Tai, Yu-Jie Huang
-
Patent number: 11667522Abstract: The present disclosure relates to a MEMS package having different trench depths, and a method of fabricating the MEMS package. In some embodiments, a cap substrate is bonded to a device substrate. The cap substrate comprises a cap substrate bonded to a device substrate. The cap substrate comprises a MEMS trench, a scribe trench, and an edge trench respectively recessed from at a front-side surface of the cap substrate. A stopper is disposed within the MEMS trench and raised from a bottom surface of the MEMS trench.Type: GrantFiled: December 2, 2020Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chuan Tai, Fan Hu
-
Publication number: 20220306452Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity.Type: ApplicationFiled: June 15, 2022Publication date: September 29, 2022Inventors: Fan Hu, Chun-Ren Cheng, Hsiang-Fu Chen, Wen-Chuan Tai
-
Patent number: 11365115Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure.Type: GrantFiled: September 3, 2019Date of Patent: June 21, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fan Hu, Chun-Ren Cheng, Hsiang-Fu Chen, Wen-Chuan Tai
-
Patent number: 11289568Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.Type: GrantFiled: May 13, 2019Date of Patent: March 29, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Wen-Chuan Tai, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Anderson Lin, Fu-Chun Huang, Chun-Ren Cheng, Ivan Hua-Shu Wu, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
-
Patent number: 11220422Abstract: A micro-electro-mechanical system (MEMS) device includes a substrate, a proof mass, and a piezoelectric bump. The substrate has a surface. The proof mass is suspended over the surface of the substrate, wherein the proof mass is movable with respect to the substrate. The piezoelectric bump is disposed on the surface of the substrate and extends a distance from the surface of the substrate toward the proof mass.Type: GrantFiled: March 14, 2019Date of Patent: January 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Fan Hu, Wen-Chuan Tai, Hsiang-Fu Chen, Chun-Ren Cheng
-
Publication number: 20210239647Abstract: A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; a carrier substrate on the MLI structure; a first through substrate via (TSV) structure extending though the carrier substrate and configured to provide an electrical connection between the MLI structure and a separate die; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; and a microfluidic channel cap structure attached to the buried oxide layer.Type: ApplicationFiled: November 11, 2020Publication date: August 5, 2021Inventors: Allen Timothy Chang, Jui-Cheng Huang, Wen-Chuan Tai, Yu-Jie Huang
-
Publication number: 20210239688Abstract: A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; and a cap structure attached to the buried oxide layer, the cap structure comprising a microneedle.Type: ApplicationFiled: November 25, 2020Publication date: August 5, 2021Inventors: Allen Timothy Chang, Jui-Cheng Huang, Wen-Chuan Tai, Yu-Jie Huang
-
Patent number: 10981781Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.Type: GrantFiled: November 4, 2019Date of Patent: April 20, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Hsin-Ting Huang, Hsiang-Fu Chen, Wen-Chuan Tai, Chia-Ming Hung, Shao-Chi Yu, Hung-Hua Lin, Yuan-Chih Hsieh
-
Patent number: 10961118Abstract: The present disclosure relates to a micro-electro mechanical system (MEMS) package and a method of achieving differential pressure adjustment in multiple MEMS cavities at a wafer-to-wafer bonding level. In some embodiments, a ventilation trench and an isolation trench are concurrently within a capping substrate. The isolation trench isolates a silicon region and has a height substantially equal to a height of the ventilation trench. A sealing structure is formed within the ventilation trench and the isolation trench, the sealing structure filing the isolation trench and defining a vent within the ventilation trench. A device substrate is provided and bonded to the capping substrate at a first gas pressure and hermetically sealing a first cavity associated with a first MEMS device and a second cavity associated with a second MEMS device. The capping substrate is thinned to open the vent to adjust a gas pressure of the second cavity.Type: GrantFiled: September 26, 2019Date of Patent: March 30, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Chia Lee, Chin-Min Lin, Cheng San Chou, Hsiang-Fu Chen, Wen-Chuan Tai, Ching-Kai Shen, Hua-Shu Ivan Wu, Fan Hu