Patents by Inventor Wen-Chuan Tai

Wen-Chuan Tai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250122071
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity.
    Type: Application
    Filed: December 27, 2024
    Publication date: April 17, 2025
    Inventors: Fan Hu, Chun-Ren Cheng, Hsiang-Fu Chen, Wen-Chuan Tai
  • Patent number: 12269735
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chuan Tai, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu, Fan Hu
  • Publication number: 20250058353
    Abstract: A micro-electromechanical-system (MEMS) device may include a capacitive micromachined ultrasonic transducer (CMUT) that includes an actuation membrane and a sensing dielectric layer that are spaced apart by a cavity. The sensing dielectric layer may be formed such that the thickness of the sensing dielectric layer may extend the operational of the CMUT while enabling the CMUT to accommodate a sufficiently high direct current voltage bias for collapsed mode operation. In this way, the thickness of the sensing dielectric layer enables the CMUT to operate in the collapsed mode, which enables the CMUT to achieve greater sound pressure output relative to other operational modes and enables the frequency response of the CMUT to be adjustable, thereby enabling the frequency response to be optimized for specific use cases and applications.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 20, 2025
    Inventors: Chia-Ming HUNG, Wen-Chuan TAI, Chun-Heng CHEN, Shao-Da WANG, Hsiang-Fu CHEN
  • Patent number: 12215016
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fan Hu, Chun-Ren Cheng, Hsiang-Fu Chen, Wen-Chuan Tai
  • Publication number: 20250035623
    Abstract: A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; and a cap structure attached to the buried oxide layer, the cap structure comprising a microneedle.
    Type: Application
    Filed: July 30, 2024
    Publication date: January 30, 2025
    Inventors: Allen Timothy Chang, Jui-Cheng Huang, Wen-Chuan Tai, Yu-Jie Huang
  • Publication number: 20240410855
    Abstract: A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; a carrier substrate on the MLI structure; a first through substrate via (TSV) structure extending though the carrier substrate and configured to provide an electrical connection between the MLI structure and a separate die; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; and a microfluidic channel cap structure attached to the buried oxide layer.
    Type: Application
    Filed: July 23, 2024
    Publication date: December 12, 2024
    Inventors: Allen Timothy Chang, Jui-Cheng Huang, Wen-Chuan Tai, Yu-Jie Huang
  • Publication number: 20240375943
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Wen-Chuan Tai, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu, Fan Hu
  • Patent number: 12123871
    Abstract: A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; and a cap structure attached to the buried oxide layer, the cap structure comprising a microneedle.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Allen Timothy Chang, Jui-Cheng Huang, Wen-Chuan Tai, Yu-Jie Huang
  • Patent number: 12123846
    Abstract: A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; a carrier substrate on the MLI structure; a first through substrate via (TSV) structure extending though the carrier substrate and configured to provide an electrical connection between the MLI structure and a separate die; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; and a microfluidic channel cap structure attached to the buried oxide layer.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Allen Timothy Chang, Jui-Cheng Huang, Wen-Chuan Tai, Yu-Jie Huang
  • Publication number: 20240304580
    Abstract: A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.
    Type: Application
    Filed: May 14, 2024
    Publication date: September 12, 2024
    Inventors: WEN-CHUAN TAI, FAN HU, HSIANG-FU CHEN, LI-CHUN PENG
  • Patent number: 12015001
    Abstract: A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Chuan Tai, Fan Hu, Hsiang-Fu Chen, Li-Chun Peng
  • Publication number: 20240044889
    Abstract: A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; and a cap structure attached to the buried oxide layer, the cap structure comprising a microneedle.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 8, 2024
    Inventors: Allen Timothy Chang, Jui-Cheng Huang, Wen-Chuan Tai, Yu-Jie Huang
  • Publication number: 20240038597
    Abstract: A method and a system for detecting a semiconductor device are provided. The method comprises obtaining an image of the semiconductor device, evaluating a feature of the image, detecting a defect of the semiconductor device based on the feature, extracting a defect information for the defect, calculating a defect die ratio (DDR) in response to the defect and analyzing a relation between the DDR and the defect information.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: FAN HU, WEN-CHUAN TAI, HSIANG-FU CHEN, I-CHIEH HUANG, TZU-CHIEH WEI, KANG-YI LIEN
  • Publication number: 20230399226
    Abstract: The present disclosure relates to an integrated chip including a semiconductor device substrate and a plurality of semiconductor devices arranged along the semiconductor device substrate. A micro-electromechanical system (MEMS) layer overlies the semiconductor device substrate. The MEMS layer includes a first moveable mass and a second moveable mass. A capping layer overlies the MEMS layer. The capping layer has a first lower surface directly over the first moveable mass and a second lower surface directly over the second moveable mass. An outgas layer is on the first lower surface and directly between the first pair of sidewalls. A lower surface of the outgas layer delimits a first cavity in which the first moveable mass is arranged. The second lower surface of the capping layer delimits a second cavity in which the second moveable mass is arranged.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 14, 2023
    Inventors: Fan Hu, Wen-Chuan Tai, Li-Chun Peng, Hsiang-Fu Chen, Ching-Kai Shen, Hung-Wei Liang, Jung-Kuo Tu
  • Publication number: 20230393091
    Abstract: A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; a carrier substrate on the MLI structure; a first through substrate via (TSV) structure extending though the carrier substrate and configured to provide an electrical connection between the MLI structure and a separate die; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; and a microfluidic channel cap structure attached to the buried oxide layer.
    Type: Application
    Filed: August 17, 2023
    Publication date: December 7, 2023
    Inventors: Allen Timothy Chang, Jui-Cheng Huang, Wen-Chuan Tai, Yu-Jie Huang
  • Patent number: 11834325
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: December 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fan Hu, Chun-Ren Cheng, Hsiang-Fu Chen, Wen-Chuan Tai
  • Publication number: 20230381815
    Abstract: A method of forming a transducer includes depositing a first dielectric layer on a first electrode, patterning the first dielectric layer to form first protrusions and second protrusions, where a first diameter of each of the first protrusions is larger than a second diameter of each of the second protrusions; and bonding the first dielectric layer to a second electrode using a second dielectric layer, where sidewalls of the second dielectric layer define a cavity disposed between the first electrode and the second electrode, and where the first protrusions are disposed in the cavity.
    Type: Application
    Filed: May 24, 2022
    Publication date: November 30, 2023
    Inventors: Chi-Yuan Shih, Shih-Fen Huang, Yan-Jie Liao, Wen-Chuan Tai
  • Publication number: 20230382724
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Inventors: Wen-Chuan Tai, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu, Fan Hu
  • Publication number: 20230373780
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 23, 2023
    Inventors: Fan Hu, Chun-Ren Cheng, Hsiang-Fu Chen, Wen-Chuan Tai
  • Publication number: 20230331546
    Abstract: A MEMS package is provided. The MEMS package includes a metallization layer, a planarization structure, a MEMS device structure, a cap structure and a pressure adjustment element. The planarization structure has an inner sidewall defining a first cavity exposing the metallization layer. The MEMS device structure is bonded to the planarization structure. The MEMS device structure includes a movable element over the first cavity. The cap structure is bonded to the MEMS device structure and has an inner sidewall defining a second cavity facing the movable element. The pressure adjustment element is disposed in the second cavity.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: FAN HU, WEN-CHUAN TAI, LI-CHUN PENG, HSIANG-FU CHEN