Patents by Inventor Wen Chun Huang
Wen Chun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240363436Abstract: A method for forming a semiconductor structure is provided.Type: ApplicationFiled: July 10, 2024Publication date: October 31, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ting KO, Wen-Ju CHEN, Tai-Chun HUANG
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Publication number: 20240345428Abstract: An electronic device including an active region and a peripheral region, and includes a substrate including a first edge; a first electrode layer disposed on the substrate; a first conductive glue disposed on the substrate and in the peripheral region; a second conductive glue disposed on the substrate and in the peripheral region; an insulating glue disposed in the peripheral region and overlapped with the first conductive glue and the second conductive glue; and a first metal element fixed on the first electrode layer through the first conductive glue and the insulating glue; wherein in a top view, the insulating glue extends along an extension direction parallel to the first edge, and along the extension direction, a sum of lengths of the first conductive glue and the second conductive glue is less than a length of the insulating glue.Type: ApplicationFiled: June 25, 2024Publication date: October 17, 2024Inventors: Wen-Cheng HUANG, Bi-Ly LIN, Chia-Chun YANG, Ying-Jung WU, Chien-Wei TSENG
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Publication number: 20240339074Abstract: An electronic device includes: a circuit substrate; a first substrate overlapped with the circuit substrate; a first electronic unit attached on the first substrate; a second substrate disposed between the first substrate and the circuit substrate; a first transistor attached on the second substrate and electrically connected to the first electronic unit; and a first conductive element penetrating the second substrate, wherein the first transistor is electrically connected to the circuit substrate through the first conductive element.Type: ApplicationFiled: June 17, 2024Publication date: October 10, 2024Inventors: Yi-Hua HSU, Ker-Yih KAO, Ming-Chun TSENG, Mu-Fan CHANG, Wen-Lin HUANG
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Patent number: 12105562Abstract: A portable electronic device including a main display having a locking recess at a side edge and at least one external display detachable relative to the side edge of the main display is provided. The external display includes a body, and at least one latch pivoted to the body. The latch is pivoted to the body to be swiveled out of or into the body. An opening of the locking recess faces obliquely upward and faces away from a direction of gravity when the main display is standing, the at least one latch swiveled out of the body faces obliquely downward and faces forward the direction of gravity to be inserted into the locking recess, and the at least one external display is hung on at the side edge of the main display by a weight of the at least one external display.Type: GrantFiled: May 23, 2023Date of Patent: October 1, 2024Assignee: Acer IncorporatedInventors: Yu-Shih Wang, Yi-Ta Huang, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai
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Patent number: 12094790Abstract: A testkey structure for semiconductor device includes a substrate, a gate structure disposed on the substrate, and a plurality of first dummy gate structures disposed on the substrate and arranged around the gate structure. A bottom surface of the gate structure is lower than bottom surfaces of the first dummy gate structures. A top surface of the gate structure is flush with top surfaces of the first dummy gate structures.Type: GrantFiled: March 30, 2022Date of Patent: September 17, 2024Assignee: United Semiconductor (Xiamen) Co., Ltd.Inventors: Zhi Xiang Qiu, Rong He, Hailong Gu, Chin-Chun Huang, Wen Yi Tan
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Patent number: 12094820Abstract: A semiconductor device includes a patterned metal layer on a substrate, via conductors on the patterned metal layer, first inter-metal dielectric (IMD) patterns embedded in the patterned metal layer, and a second IMD pattern surrounding the patterned metal layer. Preferably, the first IMD patterns are between and without overlapping the via conductors in a top view.Type: GrantFiled: July 21, 2023Date of Patent: September 17, 2024Assignee: United Semiconductor (Xiamen) Co., Ltd.Inventors: Bin Guo, Hailong Gu, Chin-Chun Huang, Wen Yi Tan
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Publication number: 20240304657Abstract: A semiconductor device includes a substrate, a first gate, a plurality of second gates and a resistor. The substrate is defined with an active region and a resistor region. The first gate is disposed in the active region. The first gate has a first length extending along a first direction and a second length extending along a second direction. The plurality of second gates are disposed in the resistor region. Each of the second gates has a third length extending along the first direction and a fourth length extending along the second direction. The first length is equal to the third length, and the second length is equal to the fourth length. The resistor is disposed on the plurality of second gates.Type: ApplicationFiled: March 29, 2023Publication date: September 12, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Chun Teng, Ming-Che Tsai, Ping-Chia Shih, Yi-Chang Huang, Wen-Lin Wang, Yu-Fan Hu, Ssu-Yin Liu, Yu-Nong Chen, Pei-Tsen Shiu, Cheng-Tzung Tsai
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Patent number: 12087641Abstract: A method for forming a semiconductor structure is provided. The method includes forming first and second fin structures, wherein each of the first and the second fin structurez include first semiconductor layers and second semiconductor layers alternatingly stacked, and forming a first mask structure to cover the second fin structure. The first mask structure includes a first dielectric layer and a second dielectric layer over the first mask structure, and the first dielectric layer and the second dielectric layer are made of different materials. The method also includes forming a first source/drain feature in the first fin structure, removing the first mask structure, forming a second source/drain feature in the second fin structure, removing the first semiconductor layers of the first fin structure and the second fin structure, thereby forming first nanostructures and second nanostructures, and forming a gate stack around the first and second nanostructures.Type: GrantFiled: April 22, 2021Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ting Ko, Wen-Ju Chen, Tai-Chun Huang
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Patent number: 12087627Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.Type: GrantFiled: July 21, 2022Date of Patent: September 10, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
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Patent number: 12087687Abstract: A semiconductor device includes a resistor disposed on a second etching stop layer in the resistor forming region. A fourth interlayer dielectric layer covers the resistor and the second etch stop layer. A first via is located in the fourth interlayer dielectric layer and is electrically connected to a terminal of the resistor. By forming the resistor in BEOL process, the problem of the contact stop depth difference that affects the process window and causes the reduced yield can be improved.Type: GrantFiled: December 20, 2021Date of Patent: September 10, 2024Assignee: United Semiconductor (Xiamen) Co., Ltd.Inventors: Wei-Chun Chang, You-Di Jhang, Chin-Chun Huang, Wen Yi Tan
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Publication number: 20240296890Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.Type: ApplicationFiled: May 13, 2024Publication date: September 5, 2024Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
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Patent number: 12077873Abstract: A method for manufacturing nitride catalyst is provided, which includes putting a Ru target and an M target into a nitrogen-containing atmosphere, in which M is Ni, Co, Fe, Mn, Cr, V, Ti, Cu, or Zn. The method also includes providing powers to the Ru target and the M target, respectively. The method also includes providing ions to bombard the Ru target and the M target for depositing MxRuyN2 on a substrate by sputtering, wherein 0<x<1.3, 0.7<y<2, and x+y=2, wherein MxRuyZ2 is cubic crystal system or amorphous.Type: GrantFiled: November 30, 2020Date of Patent: September 3, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Kuo-Hsin Lin, Li-Duan Tsai, Wen-Hsuan Chao, Chiu-Ping Huang, Pin-Hsin Yang, Hsiao-Chun Huang, Jiunn-Nan Lin, Yu-Ming Lin
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Patent number: 12080614Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface; a semiconductor die mounted on the top surface of the substrate; and a two-part lid mounted on a perimeter of the top surface of the substrate and housing the semiconductor die. The lid comprises an annular lid base and a cover plate removably installed on the annular lid base. The semiconductor package can be uncovered by removing the cover plate and a forced cooling module can be installed in place of the cover plate.Type: GrantFiled: October 5, 2021Date of Patent: September 3, 2024Assignee: MEDIATEK INC.Inventors: Shih-Chao Chiu, Chi-Yuan Chen, Wen-Sung Hsu, Ya-Jui Hsieh, Yao-Pang Hsu, Wen-Chun Huang
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Patent number: 12061410Abstract: A camera device with image compensation and autofocus function, comprising a first carrying member, a second carrying member, a camera module, a first optical compensation component, a third carrying member, and an autofocus component. The second carrying member is movably assembled to the first carrying member. The first optical compensation component comprises a first force interaction member disposed at the first carrying member and a second force interaction member disposed at the second carrying member, which generate force interaction, allowing the second carrying member to move in the direction of a first axis or/and a second axis intersecting with an optical axis of the optical lens for optical compensation for the optical lens. The third carrying member bears the optical lens and is movably disposed on the second carrying member. The third carrying member could move along an optical axis of the optical lens.Type: GrantFiled: January 21, 2022Date of Patent: August 13, 2024Assignee: Lanto Electronic LimitedInventors: Fu-Yuan Wu, Tao-Chun Chen, Wen-Yen Huang, Meng-Ting Lin, Shang-Yu Hsu
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Patent number: 12044914Abstract: An electronic device including an active region and a peripheral region, and includes a substrate including a first edge and a second edge; a first electrode layer disposed on the substrate; a first conductive glue disposed on the substrate and in the peripheral region; a second conductive glue disposed on the substrate and in the peripheral region; an insulating glue overlapped with the first conductive glue and the second conductive glue; and a first metal element fixed on the first electrode layer through the first conductive glue and the insulating glue; wherein in a top view, the insulating glue is disposed in the peripheral region and extends along an extension direction parallel to the first edge, and along the extension direction, a first distance between the first conductive glue and the second edge is greater than a second distance between the second conductive glue and the second edge.Type: GrantFiled: October 27, 2023Date of Patent: July 23, 2024Assignee: INNOLUX CORPORATIONInventors: Wen-Cheng Huang, Bi-Ly Lin, Chia-Chun Yang, Ying- Jung Wu, Chien-Wei Tseng
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Patent number: 12039919Abstract: An electronic device includes: a circuit board; a plurality of diodes disposed on a first surface of the circuit board; a plurality of first driving circuits disposed on the first surface of the circuit board and electrically connected to the plurality of diodes; and a plurality of second driving circuits electrically connected to the plurality of first driving circuits, wherein a part of the plurality of second driving circuits are disposed on a first substrate, and another part of the second driving circuits are disposed on a second substrate.Type: GrantFiled: April 5, 2023Date of Patent: July 16, 2024Assignee: INNOLUX CORPORATIONInventors: Yi-Hua Hsu, Ker-Yih Kao, Ming-Chun Tseng, Mu-Fan Chang, Wen-Lin Huang
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Publication number: 20230367942Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Chia-Ping CHIANG, Ming-Hui CHIH, Chih-Wei HSU, Ping-Chieh WU, Ya-Ting CHANG, Tsung-Yu WANG, Wen-Li CHENG, Hui En YIN, Wen-Chun HUANG, Ru-Gun LIU, Tsai-Sheng GAU
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Patent number: 11790145Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: GrantFiled: June 29, 2022Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
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Publication number: 20220335192Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: ApplicationFiled: June 29, 2022Publication date: October 20, 2022Inventors: Chia-Ping CHIANG, Ming-Hui CHIH, Chih-Wei HSU, Ping-Chieh WU, Ya-Ting CHANG, Tsung-Yu WANG, Wen-Li CHENG, Hui En YIN, Wen-Chun HUANG, Ru-Gun LIU, Tsai-Sheng GAU
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Patent number: 11392742Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: GrantFiled: October 5, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau