Abstract: The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.

Abstract: An electronic device is provided. The electronic device includes a frame, a backlight module, a working panel, and a spacer. The backlight module is disposed in the frame. The working panel is disposed on the frame. The spacer is disposed between the frame and the working panel. At least a portion of the working panel and at least a portion of the spacer are in direct contact with an adhesive.

Abstract: A battery module capable of suppressing spread of battery fire including a case, a plurality of battery packs, a plurality of temperature sensors, an energy consumption module and a controller. The case forms an accommodation space, and the battery packs is accommodated in the accommodation space. The temperature sensors are dispersedly configured to the accommodation space, and the temperature sensors respectively detect an ambient temperature around configure locations. The controller is coupled to the temperature sensors, and when the ambient temperature detected by one of the temperature sensors is greater than or equal to a first specific temperature range, the controller controls the energy consumption module to consume a battery capacity of at least one battery pack around the one of the temperature sensors.

Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.

Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

Abstract: The present invention discloses a display panel and a display device. The display panel comprises a plurality of common electrode blocks and a plurality of display regions. During a display period, one or more common electrode blocks corresponding to one of the display regions which is to be displayed during the display period are coupled to a common voltage; and during the display period, one or more of the common electrode blocks corresponding to the display regions which are not to be displayed during the display period are kept in a floating state.

Abstract: A camera device with image compensation and autofocus function, comprising a first carrying member, a second carrying member, a camera module, a first optical compensation component, a third carrying member, and an autofocus component. The second carrying member is movably assembled to the first carrying member. The first optical compensation component comprises a first force interaction member disposed at the first carrying member and a second force interaction member disposed at the second carrying member, which generate force interaction, allowing the second carrying member to move in the direction of a first axis or/and a second axis intersecting with an optical axis of the optical lens for optical compensation for the optical lens. The third carrying member bears the optical lens and is movably disposed on the second carrying member. The third carrying member could move along an optical axis of the optical lens.

Abstract: A method for forming a semiconductor structure is provided.

Abstract: An electronic device including an active region and a peripheral region, and includes a substrate including a first edge; a first electrode layer disposed on the substrate; a first conductive glue disposed on the substrate and in the peripheral region; a second conductive glue disposed on the substrate and in the peripheral region; an insulating glue disposed in the peripheral region and overlapped with the first conductive glue and the second conductive glue; and a first metal element fixed on the first electrode layer through the first conductive glue and the insulating glue; wherein in a top view, the insulating glue extends along an extension direction parallel to the first edge, and along the extension direction, a sum of lengths of the first conductive glue and the second conductive glue is less than a length of the insulating glue.

Abstract: An electronic device includes: a circuit substrate; a first substrate overlapped with the circuit substrate; a first electronic unit attached on the first substrate; a second substrate disposed between the first substrate and the circuit substrate; a first transistor attached on the second substrate and electrically connected to the first electronic unit; and a first conductive element penetrating the second substrate, wherein the first transistor is electrically connected to the circuit substrate through the first conductive element.

Abstract: A portable electronic device including a main display having a locking recess at a side edge and at least one external display detachable relative to the side edge of the main display is provided. The external display includes a body, and at least one latch pivoted to the body. The latch is pivoted to the body to be swiveled out of or into the body. An opening of the locking recess faces obliquely upward and faces away from a direction of gravity when the main display is standing, the at least one latch swiveled out of the body faces obliquely downward and faces forward the direction of gravity to be inserted into the locking recess, and the at least one external display is hung on at the side edge of the main display by a weight of the at least one external display.

Abstract: A testkey structure for semiconductor device includes a substrate, a gate structure disposed on the substrate, and a plurality of first dummy gate structures disposed on the substrate and arranged around the gate structure. A bottom surface of the gate structure is lower than bottom surfaces of the first dummy gate structures. A top surface of the gate structure is flush with top surfaces of the first dummy gate structures.

Abstract: A semiconductor device includes a patterned metal layer on a substrate, via conductors on the patterned metal layer, first inter-metal dielectric (IMD) patterns embedded in the patterned metal layer, and a second IMD pattern surrounding the patterned metal layer. Preferably, the first IMD patterns are between and without overlapping the via conductors in a top view.

Abstract: A semiconductor device includes a substrate, a first gate, a plurality of second gates and a resistor. The substrate is defined with an active region and a resistor region. The first gate is disposed in the active region. The first gate has a first length extending along a first direction and a second length extending along a second direction. The plurality of second gates are disposed in the resistor region. Each of the second gates has a third length extending along the first direction and a fourth length extending along the second direction. The first length is equal to the third length, and the second length is equal to the fourth length. The resistor is disposed on the plurality of second gates.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming first and second fin structures, wherein each of the first and the second fin structurez include first semiconductor layers and second semiconductor layers alternatingly stacked, and forming a first mask structure to cover the second fin structure. The first mask structure includes a first dielectric layer and a second dielectric layer over the first mask structure, and the first dielectric layer and the second dielectric layer are made of different materials. The method also includes forming a first source/drain feature in the first fin structure, removing the first mask structure, forming a second source/drain feature in the second fin structure, removing the first semiconductor layers of the first fin structure and the second fin structure, thereby forming first nanostructures and second nanostructures, and forming a gate stack around the first and second nanostructures.

Abstract: A semiconductor device includes a resistor disposed on a second etching stop layer in the resistor forming region. A fourth interlayer dielectric layer covers the resistor and the second etch stop layer. A first via is located in the fourth interlayer dielectric layer and is electrically connected to a terminal of the resistor. By forming the resistor in BEOL process, the problem of the contact stop depth difference that affects the process window and causes the reduced yield can be improved.

Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A method for manufacturing nitride catalyst is provided, which includes putting a Ru target and an M target into a nitrogen-containing atmosphere, in which M is Ni, Co, Fe, Mn, Cr, V, Ti, Cu, or Zn. The method also includes providing powers to the Ru target and the M target, respectively. The method also includes providing ions to bombard the Ru target and the M target for depositing MxRuyN2 on a substrate by sputtering, wherein 0<x<1.3, 0.7<y<2, and x+y=2, wherein MxRuyZ2 is cubic crystal system or amorphous.

Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface; a semiconductor die mounted on the top surface of the substrate; and a two-part lid mounted on a perimeter of the top surface of the substrate and housing the semiconductor die. The lid comprises an annular lid base and a cover plate removably installed on the annular lid base. The semiconductor package can be uncovered by removing the cover plate and a forced cooling module can be installed in place of the cover plate.