Patents by Inventor Wen Chun Huang

Wen Chun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10410863
    Abstract: The present disclosure provides a method that includes forming a first pattern feature and a second pattern feature over a material layer by a first photolithographic process. The method also includes forming a first spacer feature on a sidewall of the first pattern feature and a second spacer feature on a sidewall of the second pattern feature. Additionally, the method includes forming a third pattern feature on the material layer between the first spacer feature and the second spacer feature by a second photolithographic process. In addition, the method includes removing the first and second spacer features to expose a portion of the material layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: September 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Publication number: 20190271891
    Abstract: A pixel structure includes a substrate, first and second gate lines, first and second data lines, and at least one pixel unit. The first and second gate lines and the first and second data lines are over the substrate and intersect with each other. The pixel unit is disposed on the substrate. The pixel unit includes first and second active devices, a common electrode, and first and second pixel electrodes. The first and second active devices are electrically connected to the first data line, and electrically connected to the first and second gate lines respectively. The common electrode is connected to a common potential source. The first and second pixel electrodes are over the common electrode and electrically connected to the first and second active devices respectively. At least one second branch electrode of the second pixel electrode shrinks from its one side to another side.
    Type: Application
    Filed: January 31, 2019
    Publication date: September 5, 2019
    Inventors: Sih-Yan LIN, Chia-Chun HSU, Yu-Zhang HUANG, Yen-Hua LO, Hsin-Chun HUANG, Wen-Rei GUO
  • Publication number: 20190259636
    Abstract: A method includes rotating a wafer, dispensing a liquid from a center of the wafer to an edge of the wafer to control a temperature of the wafer, and etching an etch layer of the wafer with an etchant during or after dispensing the liquid. The liquid is dispensed through a nozzle.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Manish Kumar SINGH, Bo-Wei CHOU, Jui-Ming SHIH, Wen-Yu KU, Ping-Jung HUANG, Pi-Chun YU
  • Publication number: 20190234851
    Abstract: A gas detecting device includes a casing, an optical mechanism, a gas transporting actuator, a laser module, a particle detector and an external sensing module. The casing includes a chamber, an inlet, an outlet and a communication channel. The optical mechanism is disposed in the chamber. The optical mechanism includes an airflow channel and a light-beam channel. The airflow channel is in fluid communication with the at least one inlet and the outlet. The light-beam channel is in communication with the airflow channel. The gas transporting actuator is disposed on the optical mechanism. The laser module is disposed in the optical mechanism for emitting a light beam to the airflow channel. The particle detector detects sizes and a concentration of the suspended particles in the air. The external sensing module is installed in the communication channel to measure the air.
    Type: Application
    Filed: December 18, 2018
    Publication date: August 1, 2019
    Applicant: Microjet Technology Co., Ltd.
    Inventors: Hao-Jan MOU, Hung-Chun HU, Young-Chih KUO, Jui-Yuan CHU, Chien-Chih HUANG, Wen-Hsiung LIU, Yi-Cheng HUANG, Wei-Chen LIAO, Chi-Chiang HSIEH, Chi-Feng HUANG, Yung-Lung HAN
  • Patent number: 10360339
    Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Chun Wang, Ching-Hsu Chang, Chun-Hung Wu, Cheng Kun Tsai, Feng-Ju Chang, Feng-Lung Lin, Ming-Hsuan Wu, Ping-Chieh Wu, Ru-Gun Liu, Wen-Chun Huang, Wen-Hao Liu
  • Publication number: 20190190904
    Abstract: A method and system of authenticating a user are provided. A request for a resource is received from a user device. A predefined number is received. A first number and a second number are created. A first discrete logarithm based on the first number and the predefined number is determined and sent to the user device, together with the second number. A second discrete logarithm is received from the user device. A first pass code is calculated via a third discrete logarithm, based on the second discrete logarithm, the first number, and the predefined number. A second pass code is received via a fourth discrete logarithm, based on the first discrete logarithm, the third number, and the predefined number. Upon determining that the first pass code is identical to the second pass code, the user device is allowed to access a resource associated with the computing device.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 20, 2019
    Inventors: Yi-Chun Chen, Wen-Ping Chi, Chao Yuan Huang, Ting-Yi Wang
  • Publication number: 20190190903
    Abstract: A method and system of authenticating a user are provided. A request for a resource is received by a server, from a user device. A predefined number is received from the user device. A first number and a second number are created. The first number is sent to the user device. A first discrete logarithm is determined based on a challenge code and the first number and sent to the user device. A first pass code is calculated via a second discrete logarithm based on the first discrete logarithm, the predefined number, and the first number. A second pass code based on the second discrete logarithm, is received from the user device. The first pass code is compared to the second pass code. Upon determining that the first pass code is identical to the second pass code, the user device is allowed access a resource associated with the computing device.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 20, 2019
    Inventors: Yi-Chun Chen, Wen-Ping Chi, Chao Yuan Huang, Ting-Yi Wang
  • Patent number: 10324369
    Abstract: Embodiments of the present disclosure provide a method of generating mandrel patterns. A mandrel pattern is generated by constructing a boundary box, initiating a plurality of lead mandrels, and extending the lead mandrels across the boundary box. When a pattern region includes holes, portions of mandrels are removed from the holes after extension of the leading mandrels.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu Wang, Nian-Fuh Cheng, Chia-Ping Chiang, Ming-Hui Chih, Wen-Chun Huang, Tsai-Sheng Gau
  • Publication number: 20190157442
    Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 23, 2019
    Inventors: Shang-Hui TU, Chih-Jen HUANG, Jui-Chun CHANG, Shin-Cheng LIN, Yu-Hao HO, Wen-Hsin LIN
  • Publication number: 20190155911
    Abstract: A method for context-aware translation is provided. The present invention may include receiving a program integrated information file (PII) associated with a graphical user interface object of with a software product. The present invention may also include indexing each element string within the PII file. The present invention may further include generating a base language general availability build of the graphical user interface object using the PII file. The present invention may also include retrieving a document object model (DOM) of each element within the base language general availability build. The present invention may further include creating a string relation table for the base language general availability build using the DOM for each element and each indexed element string within the PII file. The present invention may also include generating a string relation translation memory table for at least one language.
    Type: Application
    Filed: January 18, 2019
    Publication date: May 23, 2019
    Inventors: Chi-Ying Chang, Yi-Chun Chen, Wen-Ping Chi, Chao Yuan Huang
  • Publication number: 20190147134
    Abstract: Implementations of the disclosure provide a method of fabricating an integrated circuit (IC). The method includes receiving an IC design layout; performing optical proximity correction (OPC) process to the IC design layout to produce a corrected IC design layout; and verifying the corrected IC design layout using a machine learning algorithm. The post OPC verification includes using the machine learning algorithm to identify one or more features of the corrected IC design layout; comparing the one or more identified features to a database comprising a plurality of features; and verifying the corrected IC design layout based on labels in the database associated with the plurality of features.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chun Wang, Cheng Kun Tsai, Wen-Chun Huang, Wei-Chen Chien, Chi-Ping Liu
  • Publication number: 20190095569
    Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: CHIA-PING CHIANG, MING-HUI CHIH, CHIH-WEI HSU, PING-CHIEH WU, YA-TING CHANG, TSUNG-YU WANG, WEN-LI CHENG, HUI EN YIN, WEN-CHUN HUANG, RU-GUN LIU, TSAI-SHENG GAU
  • Publication number: 20190094710
    Abstract: Examples of optical proximity correction (OPC) based computational lithography techniques are disclosed herein. An exemplary method includes receiving an IC design layout that includes an IC feature, the IC feature specifying a mask feature for selectively exposing to radiation a portion of a photoresist disposed on a substrate; determining topographical information of an underlying layer disposed on the substrate between the photoresist and the substrate; performing an OPC process on the IC feature to generate a modified IC feature; and providing a modified IC design layout including the modified IC feature for fabricating a mask based on the modified IC design layout. The OPC process may use the topographical information of the underlying layer to compensate for an amount of radiation directed towards the portion of the photoresist so as to expose the portion of the photoresist to a target dosage of radiation.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 28, 2019
    Inventors: Hung-Chun Wang, Chi-Ping Liu, Cheng Kun Tsai, Wei-Chen Chien, Wen-Chun Huang
  • Publication number: 20190064652
    Abstract: Embodiments of the present disclosure provide a method of generating mandrel patterns. A mandrel pattern is generated by constructing a boundary box, initiating a plurality of lead mandrels, and extending the lead mandrels across the boundary box. When a pattern region includes holes, portions of mandrels are removed from the holes after extension of the leading mandrels.
    Type: Application
    Filed: August 25, 2017
    Publication date: February 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Yu Wang, Nian-Fuh Cheng, Chia-Ping Chiang, Ming-Hui Chih, Wen-Chun Huang, Tsai-Sheng Gau
  • Publication number: 20190042685
    Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.
    Type: Application
    Filed: September 17, 2018
    Publication date: February 7, 2019
    Inventors: Ken-Hsien Hsieh, Chih-Ming Lai, Ru-Gun Liu, Wen-Chun Huang, Wen-Li Cheng, Pai-Wei Wang
  • Publication number: 20180349545
    Abstract: The present disclosure relates to a method of data preparation. The method, in some embodiments, performs a first data preparation process using a data preparation element. The first data preparation process modifies a plurality of shapes of an integrated chip (IC) design that comprises a graphical representation of a layout used to fabricate an integrated chip. A plurality of additional shapes are added to the IC design using an additional shape insertion element. The plurality of additional shapes are separated from the plurality of shapes by one or more non-zero distances. A second data preparation process is performed using the data preparation element, after performing the first data preparation process. The second data preparation process modifies the plurality of additional shapes.
    Type: Application
    Filed: August 9, 2018
    Publication date: December 6, 2018
    Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Wen-Hao Liu, Cheng-Hsuan Huang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 10096544
    Abstract: The present disclosure provides an interconnect structure for a semiconductor device. The interconnect structure includes a first metal layer that contains a first metal line. The interconnect structure includes a dielectric layer located over the first metal layer. The dielectric layer contains a first sub-via electrically coupled to the first metal line and a second sub-via electrically coupled to the first sub-via. The second sub-via is different from the first sub-via. The interconnect structure includes a second metal layer located over the dielectric layer. The second metal layer contains a second metal line electrically coupled to the second sub-via. No other metal layer is located between the first metal layer and the second metal layer.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Ming Lai, Wen-Chun Huang, Ru-Gun Liu, Pi-Tsung Chen
  • Patent number: 10078718
    Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: September 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ken-Hsien Hsieh, Chih-Ming Lai, Ru-Gun Liu, Wen-Chun Huang, Wen-Li Cheng, Pai-Wei Wan
  • Patent number: 10049178
    Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Wen-Hao Liu, Cheng-Hsuan Huang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 10036948
    Abstract: The present disclosure provides a method of performing optical proximity correction (OPC). An integrated circuit (IC) design layout is received. The design layout contains a plurality of IC layout patterns. Two or more of the plurality of IC layout patterns are grouped together. The grouped IC layout patterns are dissected, or target points are set for the grouped IC layout patterns. Thereafter, an OPC process is performed based on the grouped IC layout patterns.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: July 31, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Li Cheng, Ming-Hui Chih, Ru-Gun Liu, Wen-Chun Huang