Patents by Inventor Wen Chun Huang

Wen Chun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8841049
    Abstract: The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chun Wang, Pei-Shiang Chen, Tzu-Chin Lin, Faruk Krecinic, Jeng-Horng Chen, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20140248768
    Abstract: A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Inventors: Wen-Chun Huang, Ken-Hsien Hsieh, Ming-Hui Chih, Chih-Ming Lai, Ru-Gun Liu, Ko-Bin Kao, Chii-Ping Chen, Dian-Hau Chen, Tsai-Sheng Gau, Burn Jeng Lin
  • Publication number: 20140248555
    Abstract: An extreme ultraviolet photomask comprises a reflective layer over a substrate, a capping layer over the reflective layer, a hard mask layer over the capping layer, and an absorber. The absorber is in the hard mask layer, the capping layer and the reflective layer.
    Type: Application
    Filed: May 16, 2014
    Publication date: September 4, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Hsu CHANG, Hung-Chun WANG, Boren LUO, Wen-Chun HUANG, Ru-Gun LIU
  • Patent number: 8806386
    Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Chou Cheng, Ru-Gun Liu, Josh J. H. Feng, Tsong-Hua Ou, Luke Lo, Chih-Ming Lai, Wen-Chun Huang
  • Patent number: 8764995
    Abstract: Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A planarizing process is provided to remove the absorber layer above the top surface of the hard mask layer and form an absorber in the opening, wherein the absorber is substantially co-planar with the top surface of the hard mask layer.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hsu Chang, Hung-Chun Wang, Boren Luo, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 8762899
    Abstract: A method of via patterning mask assignment for a via layer using double patterning technology, the method includes determining, using a processor, if a via of the via layer intercepts an underlying or overlaying metal structure assigned to a first metal mask. If the via intercepts the metal structure assigned to the first metal mask, assigning the via to a first via mask, wherein the first via mask aligns with the first metal mask. Otherwise, assigning the via to a second via mask, wherein the second via mask aligns with a second metal mask different from the first metal mask.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Burn Jeng Lin, Tsai-Sheng Gau, Ru-Gun Liu, Wen-Chun Huang
  • Publication number: 20140170537
    Abstract: An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern.
    Type: Application
    Filed: February 25, 2014
    Publication date: June 19, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: George Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
  • Patent number: 8751976
    Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes building a pattern bank including a pattern having an area of interest. The method further includes recognizing that the pattern of the pattern bank corresponds to a pattern of an IC design layout. The method further includes identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank. The method further includes performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect the area of interest of the pattern of the IC design layout into a plurality of segments. The method further includes after performing pattern recognition dissection, producing a modified IC design layout.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: June 10, 2014
    Inventors: Cheng-Lung Tsai, Jui-Hsuan Feng, Sheng-Wen Lin, Wen-Li Cheng, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 8745550
    Abstract: The present disclosure describes an OPC method of preparing data for forming a mask. The method includes setting a plurality of dissection points at the main feature and further includes setting a target point at the main feature. The method includes arranging the two dissection points crossing the main feature symmetrically each other. The method includes separating two adjacent dissection points at one side of the main feature by a maximum resolution of the mask writer. The method includes dividing the main feature into a plurality of segments using the dissection points. The method includes performing an OPC convergence simulation to a target point. The method includes correcting the segments belonging to an ambit of the target point and further includes correcting the segment shared by two ambits.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nian-Fuh Cheng, Yu-Po Tang, Chien-Fu Lee, Sheng-Wen Lin, Yong-Cheng Lin, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 8745554
    Abstract: The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Chou Cheng, Tsong-Hua Ou, Josh J. H. Feng, Cheng-Lung Tsai, Ru-Gun Liu, Wen-Chun Huang
  • Patent number: 8739080
    Abstract: The present disclosure describes methods of forming a mask. In an example, the method includes receiving an integrated circuit (IC) design layout, modifying the IC design layout data using an optical proximity correction (OPC) process, thereby providing an OPCed IC design layout, and modifying the OPCed IC design layout data using a mask rule check (MRC) process, wherein the MRC process corrects rule violations of the OPCed IC design layout data using a mask error enhancement factor (MEEF) index, thereby providing a MRC/OPCed IC design layout.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lung Tsai, Jui-Hsuan Feng, Sheng-Wen Lin, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20140115546
    Abstract: The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step.
    Type: Application
    Filed: October 23, 2012
    Publication date: April 24, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Hung-Chun Wang, Shao-Yun Fang, Tzu-Chin Lin, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20140109026
    Abstract: A method for performing optical proximity correction (OPC) and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first OPC modification to a mask feature of the design database is made by performing a first OPC process. The OPC process includes: dividing the mask feature into child shapes and adjusting an attribute of a child shape based on an edge placement error (EPE) factor. A first lithography simulation is performed utilizing a first set of performance indexes after making the first OPC modification, and a second OPC modification to the mask feature is made based on a result of the first lithography simulation. A second lithography simulation of the mask feature is performed utilizing a second set of performance indexes to verify the first and second OPC modifications, and the design database is provided for manufacturing.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 17, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chun Wang, Ming-Hui Chih, Yu-Po Tang, Chia-Ping Chiang, Feng-Ju Chang, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20140101624
    Abstract: The present disclosure describes a method of calibrating a contour. The method includes designing an anchor pattern, printing the anchor pattern on a substrate, collecting scanning electron microscope (SEM) data of the printed anchor pattern on the substrate, wherein the SEM data includes a SEM image of the printed anchor pattern on the substrate, converting the SEM image of the printed anchor pattern on the substrate into a SEM contour of the printed anchor pattern, analyzing the SEM contour of the printed anchor pattern, and aligning the SEM contour of the anchor pattern to form the calibrated SEM contour.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Chieh Wu, Tzu-Chin Lin, Hung-Ting Lu, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20140096778
    Abstract: A mask includes a frame, ear fasteners, a resisting portion and a covering piece. The frame is of an arcuate shape approximating a person's face curve, having two ends respectively connected with the ear fastener and an intermediate portion extending downward to form a support portion, and further provided with a projecting stud protruding inward and having a first fastening portion and a first engage portion. The resisting portion is disposed with a second engage portion to be engaged with the first engage portion for combining the resisting portion with the projecting stud. The covering piece is formed with a second fastening portion corresponding with the first fastening portion of the projecting stud. The second fastening portion of the covering piece is engaged with the first fastening portion of the projecting stud to have the covering piece mounted on the frame.
    Type: Application
    Filed: August 16, 2013
    Publication date: April 10, 2014
    Inventor: Wen-Chun Huang
  • Publication number: 20140101623
    Abstract: A method includes determining one or more potential merges corresponding to a color set Ai and a color set Aj of N color sets, represented by A1 to AN, used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers from 1 to N, and i?j. One or more potential cuts corresponding to the color set Ai and the second color set Aj are determined. An index Aij is determined according to the one or more potential merges and the one or more potential cuts. A plurality of parameters F related to the index Aij is obtained based on various values of indices fi and fj. A parameter F is selected among the plurality of parameters F based on a definition of the index Aij.
    Type: Application
    Filed: December 12, 2013
    Publication date: April 10, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pi-Tsung CHEN, Ming-Hui CHIH, Ken-Hsien HSIEH, Wei-Long WANG, Wen-Chun HUANG, Ru-Gun LIU, Tsai-Sheng GAU, Wen-Ju YANG, Gwan Sin CHANG, Yung-Sung YEN
  • Patent number: 8683392
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing an integrated circuit layout plan, the integrated circuit layout plan containing a plurality of semiconductor features. The method includes selecting a subset of the features for decomposition as part of a double patterning process. The method includes designating a relationship between at least a first feature and a second feature of the subset of the features. The relationship dictates whether the first and second features are assigned to a same photomask or separate photomasks. The designating is carried out using a pseudo feature that is part of the layout plan but does not appear on a photomask. The method may further include a double patterning conflict check process, which may include an odd-loop check process.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: March 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ken-Hsien Hsieh, Huang-Yu Chen, Jhih-Jian Wang, Cheng Kun Tsai, Tsong-Hua Ou, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 8681326
    Abstract: The present disclosure is directed generally to a method and apparatus for monitoring mask process impact on lithography performance. A method including receiving a physical wafer pattern according to a mask, extracting a mask contour from the mask, and extracting a deconvolution pattern based on the mask contour. A lithography process is simulated to create a virtual wafer pattern based on the deconvolution pattern. The virtual wafer pattern is then compared to the physical wafer pattern.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Chieh Wu, Chien-Hsun Chen, Ru-Gun Liu, Wen-Chun Huang, Chih-Ming Lai, Boren Luo
  • Patent number: 8673520
    Abstract: An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: George Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
  • Patent number: 8656319
    Abstract: A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: February 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Cheng Kuo, Ching-Che Tsai, Tzu-Chun Lo, Chih-Wei Hsu, Hua-Tai Lin, Tsai-Sheng Gau, Wen-Chun Huang, Chih-Shiang Chou, Hsin-Chang Lee, Kuei Shun Chen