Patents by Inventor Wen Chun Huang

Wen Chun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9390217
    Abstract: A method for performing optical proximity correction (OPC) and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first OPC modification to a mask feature of the design database is made by performing a first OPC process. The OPC process includes: dividing the mask feature into child shapes and adjusting an attribute of a child shape based on an edge placement error (EPE) factor. A first lithography simulation is performed utilizing a first set of performance indexes after making the first OPC modification, and a second OPC modification to the mask feature is made based on a result of the first lithography simulation. A second lithography simulation of the mask feature is performed utilizing a second set of performance indexes to verify the first and second OPC modifications, and the design database is provided for manufacturing.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: July 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chun Wang, Ming-Hui Chih, Yu-Po Tang, Chia-Ping Chiang, Feng-Ju Chang, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20160162627
    Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 9, 2016
    Inventors: Hung-Chun Wang, Ching-Hsu Chang, Chun-Hung Wu, Cheng Kun Tsai, Feng-Ju Chang, Feng-Lung Lin, Ming-Hsuan WU, Ping-Chieh Wu, Ru-Gun Liu, Wen-Chun Huang, Wen-Hao Liu
  • Patent number: 9362119
    Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of: forming a plurality of first features over the target material layer using a first sub-layout, with each first feature having sidewalls; forming a plurality of spacer features, with each spacer feature conforming to the sidewalls of one of the first features and having a spacer width; and forming a plurality of second features over the target material layer using a second sub-layout. The method further includes steps of removing the plurality of spacer features from around each first feature and patterning the target material layer using the plurality of first features and the plurality of second features. Other methods and associated patterned semiconductor wafers are also provided herein.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 9336986
    Abstract: The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chun Wang, Pei-Shiang Chen, Tzu-Chin Lin, Faruk Krecinic, Jeng-Horng Chen, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9298083
    Abstract: An extreme ultraviolet photomask comprises a reflective layer over a substrate, a capping layer over the reflective layer, a hard mask layer over the capping layer, and an absorber. The absorber is in the hard mask layer, the capping layer and the reflective layer.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: March 29, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Hsu Chang, Hung-Chun Wang, Boren Luo, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9280041
    Abstract: A method of photolithography including coupling a first aperture to a lithography system, then performing a first illumination process to form a first pattern on a layer of a substrate using the first aperture, thereafter coupling a second aperture to the lithography system, and performing a second illumination process to form a second pattern on the layer of the substrate using the second aperture. The first aperture includes a first pair and a second pair of radiation-transmitting regions. The second aperture includes a second plate having a third pair and a fourth pair of radiation-transmitting regions.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Cheng Wang, Hung Chang Hsieh, Shih-Che Wang, Ping Chieh Wu, Wen-Chun Huang, Ming-Chang Wen
  • Publication number: 20160063169
    Abstract: A method of determining colorability of a layout includes generating a conflict diagram based on circuit information. The conflict diagram includes a plurality of nodes, each node of the plurality of nodes is connected to at least another node of the plurality of nodes by a link, and each node of the plurality of nodes has a degree equal to a number of links connected to the node. The method includes setting a degree of each anchor node within the conflict diagram to a value of n, where n is equal to a number of mask usable to manufacture the layout. The method further includes excluding, using a processor, nodes having a degree less than n from the conflict diagram. The method further includes performing a color status check on the conflict diagram after the excluding; and determining whether the layout is colorable based on the performed color status check.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 3, 2016
    Inventors: Nien-Yu TSAI, Chin-Chang HSU, Wen-Chun HUANG, Wen-Ju YANG
  • Patent number: 9262578
    Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chun Wang, Ching-Hsu Chang, Feng-Ju Chang, Chun-Hung Wu, Ping-Chieh Wu, Wen-Hao Liu, Ming-Hsuan Wu, Feng-Lung Lin, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20160019333
    Abstract: A method of determining whether a layout is colorable includes assigning nodes to polygon features of the layout. The method includes designating nodes as being adjacent nodes for nodes separated by less than a minimum pitch. The method includes iteratively removing nodes having less than three adjacent nodes from consideration to identify a node arrangement, wherein all nodes in the node arrangement have at least three adjacent nodes. The method includes determining whether the layout is colorable based on the node arrangement. Determining whether the layout is colorable includes independently assessing each internal node of node arrangement to determine whether each internal node of the node arrangement is colorable. The method includes generating a colored layout design for fabrication of the semiconductor device if each internal node of the node arrangement is colorable; and modifying the layout if at least one internal node of the node arrangement is not colorable.
    Type: Application
    Filed: October 1, 2015
    Publication date: January 21, 2016
    Inventors: Wen-Li CHENG, Ming-Hui CHIH, Chia-Ping CHIANG, Ken-Hsien HSIEH, Tsong-Hua OU, Wen-Chun HUANG, Ru-Gun LIU
  • Patent number: 9209048
    Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including mounting a die to a top surface of a substrate to form a device, encapsulating the die and top surface of the substrate in a mold compound, the mold compound having a first thickness over the die, and removing a portion, but not all, of the thickness of the mold compound over the die. The method further includes performing further processing on the device, and removing the remaining thickness of the mold compound over the die.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chun Huang, Chien-Chen Li, Kuo-Chio Liu, Ruey-Yun Shiue, Hsi-Kuei Cheng, Chih-Hsien Lin, Jing-Cheng Lin, Hsiang-Tai Lu, Tzi-Yi Shieh
  • Publication number: 20150331333
    Abstract: The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location.
    Type: Application
    Filed: July 24, 2015
    Publication date: November 19, 2015
    Inventors: Ching-Hsu Chang, Nian-Fuh Cheng, Chih-Shiang Chou, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9189588
    Abstract: Methods and systems for design of integrated circuits including performing OPC are discussed. In one embodiment, design data having a geometric feature is provided. A base feature is formed from the geometric feature, which has a substantially linear edge. A pseudo dissection point is determined on the base feature. Add or trim a polygon from the base feature to form a modified feature. An OPC process is performed on the modified feature to generate an output design. The output design is used to fabricate a semiconductor device on a semiconductor substrate.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: November 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Li Cheng, Ming-Hui Chih, Yu-Po Tang, Chia-Ping Chiang, Cheng-Lung Tsai, Sheng-Wen Lin, Kuei-Liang Lu, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9176373
    Abstract: A system and method of decomposing a single photoresist mask pattern to three photoresist mask patterns. The system and method assign nodes to polygon features on the single photoresist mask pattern, designate nodes as being adjacent nodes for those nodes that are less than a predetermined distance apart, iteratively remove nodes having 2 or less adjacent nodes until no nodes having 2 or less adjacent nodes remain, identify one or more internal nodes, map photoresist mask pattern designations (colors) to the internal nodes, and replace and map a color to each of the nodes removed by the temporarily removing nodes, such that each node does not have an adjacent node of the same color.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: November 3, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Li Cheng, Ming-Hui Chih, Chia-Ping Chiang, Ken-Hsien Hsieh, Tsong-Hua Ou, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20150311063
    Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of: forming a plurality of first features over the target material layer using a first sub-layout, with each first feature having sidewalls; forming a plurality of spacer features, with each spacer feature conforming to the sidewalls of one of the first features and having a spacer width; and forming a plurality of second features over the target material layer using a second sub-layout. The method further includes steps of removing the plurality of spacer features from around each first feature and patterning the target material layer using the plurality of first features and the plurality of second features. Other methods and associated patterned semiconductor wafers are also provided herein.
    Type: Application
    Filed: April 25, 2014
    Publication date: October 29, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Publication number: 20150310158
    Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.
    Type: Application
    Filed: June 2, 2014
    Publication date: October 29, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chun Wang, Ching-Hsu Chang, Feng-Ju Chang, Chun-Hung Wu, Ping-Chieh Wu, Wen-Hao Liu, Ming-Hsuan Wu, Feng-Lung Lin, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9165095
    Abstract: A method performed by a computer processing system includes receiving a design pattern for an integrated circuit, applying a function to the design pattern to generate a model contour, generating a plurality of Optical Proximity Correction (OPC) target points along the model contour, adjusting the design pattern to create an adjusted pattern, and performing a simulation on the adjusted pattern to create a simulated contour.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hui Chih, Wen-Li Cheng, Yu-Po Tang, Ping-Chieh Wu, Chia-Ping Chiang, Yong-Cheng Lin, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9165106
    Abstract: The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chun Wang, Shao-Yun Fang, Tzu-Chin Lin, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20150242562
    Abstract: The present disclosure provides a method for pattern correction for electron-beam (e-beam) lithography. In accordance with some embodiments, the method includes splitting a plurality of patterns into a plurality of pattern types; performing model fittings to determine a plurality of models for the plurality of pattern types respectively; and performing a pattern correction to an integrated circuit (IC) layout using the plurality of models.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 27, 2015
    Applicant: Taiwan Semiconductor Manfacturing Company, Ltd.
    Inventors: Hung-Chun WANG, Hsu-Ting HUANG, Wen-Chun HUANG, Ru-Gun LIU
  • Publication number: 20150228542
    Abstract: A method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel. The mandrel is then removed from the semiconductor substrate. After removing the mandrel, the oxidized region is used to pattern an underlying layer formed on the semiconductor substrate.
    Type: Application
    Filed: April 28, 2015
    Publication date: August 13, 2015
    Inventors: Wei-Chao Chiu, Chen-Yu Chen, Chih-Ming Lai, Ming-Feng Shieh, Nian-Fuh Cheng, Ru-Gun Liu, Wen-Chun Huang
  • Patent number: 9091930
    Abstract: The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hsu Chang, Nian-Fuh Cheng, Chih-Shiang Chou, Wen-Chun Huang, Ru-Gun Liu