Patents by Inventor Wen Chun Huang

Wen Chun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150187607
    Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including mounting a die to a top surface of a substrate to form a device, encapsulating the die and top surface of the substrate in a mold compound, the mold compound having a first thickness over the die, and removing a portion, but not all, of the thickness of the mold compound over the die. The method further includes performing further processing on the device, and removing the remaining thickness of the mold compound over the die.
    Type: Application
    Filed: May 13, 2014
    Publication date: July 2, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chun Huang, Chien-Chen Li, Kuo-Chio Liu, Ruey-Yun Shiue, Hsi-Kuei Cheng, Chih-Hsien Lin, Jing-Cheng Lin, Hsiang-Tai Lu, Tzi-Yi Shieh
  • Publication number: 20150161321
    Abstract: Methods and systems for design of integrated circuits including performing OPC are discussed. In one embodiment, design data having a geometric feature is provided. A base feature is formed from the geometric feature, which has a substantially linear edge. A pseudo dissection point is determined on the base feature. Add or trim a polygon from the base feature to form a modified feature. An OPC process is performed on the modified feature to generate an output design. The output design is used to fabricate a semiconductor device on a semiconductor substrate.
    Type: Application
    Filed: December 10, 2013
    Publication date: June 11, 2015
    Inventors: Wen-Li Cheng, Ming-Hui Chih, Yu-Po Tang, Chia-Ping Chiang, Cheng-Lung Tsai, Sheng-Wen Lin, Kuei-Liang Lu, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20150149969
    Abstract: The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step.
    Type: Application
    Filed: February 2, 2015
    Publication date: May 28, 2015
    Inventors: Hung-Chun Wang, Shao-Yun Fang, Tzu-Chin Lin, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20150143304
    Abstract: A method performed by a computer processing system includes receiving a design pattern for an integrated circuit, applying a function to the design pattern to generate a model contour, generating a plurality of Optical Proximity Correction (OPC) target points along the model contour, adjusting the design pattern to create an adjusted pattern, and performing a simulation on the adjusted pattern to create a simulated contour.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hui Chih, Wen-Li Cheng, Yu-Po Tang, Ping-Chieh Wu, Chia-Ping Chiang, Yong-Cheng Lin, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9026955
    Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Feng-Ju Chang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9026957
    Abstract: An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
  • Patent number: 9023695
    Abstract: The present disclosure provides a method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel. The mandrel is then removed from the semiconductor substrate. After removing the mandrel, the oxidized region is used to pattern an underlying layer formed on the semiconductor substrate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chao Chiu, Nian-Fuh Cheng, Chen-Yu Chen, Ming-Feng Shieh, Chih-Ming Lai, Wen-Chun Huang, Ru-Gun Lin
  • Publication number: 20150106773
    Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 16, 2015
    Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Feng-Ju Chang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20150106779
    Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 16, 2015
    Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Wen-Hao Liu, Cheng-Hsuan Huang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9003336
    Abstract: A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chun Huang, Ken-Hsien Hsieh, Ming-Hui Chih, Chih-Ming Lai, Ru-Gun Liu, Ko-Bin Kao, Chii-Ping Chen, Dian-Hau Chen, Tsai-Sheng Gau, Burn Jeng Lin
  • Patent number: 8959460
    Abstract: A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: February 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chun Huang, Ming-Hui Chih, Chia-Ping Chiang, Ru-Gun Liu, Tsai-Sheng Gau, Jia-Guei Jou, Chih-Chung Huang, Dong-Hsu Cheng, Yung-Pei Chin
  • Patent number: 8954899
    Abstract: The present disclosure describes a method of calibrating a contour. The method includes designing an anchor pattern, printing the anchor pattern on a substrate, collecting scanning electron microscope (SEM) data of the printed anchor pattern on the substrate, wherein the SEM data includes a SEM image of the printed anchor pattern on the substrate, converting the SEM image of the printed anchor pattern on the substrate into a SEM contour of the printed anchor pattern, analyzing the SEM contour of the printed anchor pattern, and aligning the SEM contour of the anchor pattern to form the calibrated SEM contour.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Chieh Wu, Tzu-Chin Lin, Hung-Ting Lu, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20150040082
    Abstract: A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMAPNY, LTD.
    Inventors: Wen-Chun HUANG, Ming-Hui CHIH, Chia-Ping CHIANG, Ru-Gun LIU, Tsai-Sheng GAU, Jia-Guei JOU, Chih-Chung HUANG, Dong-Hsu CHENG, Yung-Pei CHIN
  • Publication number: 20150040088
    Abstract: Among other things, one or more systems and techniques for generating or implementing a hybrid design rule set are provide herein. A set of color design rules and a set of color agnostic design rules are generated and exposed for selective design rule assignment. In an embodiment, a first color design rule is assigned to a first polygon. In an embodiment, a first color agnostic design rule is assigned to a second polygon. In this way, color design rules and color agnostic design rules are selectively applied to polygons of a design layout. Color design rules are selected for space and design efficiency. Color agnostic rules are selected for conservative design layout for design ease. A design rule checking stage and a design rule fixing stage are performed such that the design layout is compliant after color decomposition without a second design rule fixing stage.
    Type: Application
    Filed: October 25, 2013
    Publication date: February 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-I Huang, Wen-Hao Chen, Wen-Chun Huang
  • Publication number: 20150040083
    Abstract: A system and method of decomposing a single photoresist mask pattern to three photoresist mask patterns. The system and method assign nodes to polygon features on the single photoresist mask pattern, designate nodes as being adjacent nodes for those nodes that are less than a predetermined distance apart, iteratively remove nodes having 2 or less adjacent nodes until no nodes having 2 or less adjacent nodes remain, identify one or more internal nodes, map photoresist mask pattern designations (colors) to the internal nodes, and replace and map a color to each of the nodes removed by the temporarily removing nodes, such that each node does not have an adjacent node of the same color.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Li CHENG, Ming-Hui CHIH, Chia-Ping CHIANG, Ken-Hsien HSIEH, Tsong-Hua OU, Wen-Chun HUANG, Ru-Gun LIU
  • Patent number: 8949758
    Abstract: Among other things, one or more systems and techniques for generating or implementing a hybrid design rule set are provide herein. A set of color design rules and a set of color agnostic design rules are generated and exposed for selective design rule assignment. In an embodiment, a first color design rule is assigned to a first polygon. In an embodiment, a first color agnostic design rule is assigned to a second polygon. In this way, color design rules and color agnostic design rules are selectively applied to polygons of a design layout. Color design rules are selected for space and design efficiency. Color agnostic rules are selected for conservative design layout for design ease. A design rule checking stage and a design rule fixing stage are performed such that the design layout is compliant after color decomposition without a second design rule fixing stage.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-I Huang, Wen-Hao Chen, Wen-Chun Huang
  • Patent number: 8949749
    Abstract: The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chun Wang, Shao-Yun Fang, Tzu-Chin Lin, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 8943445
    Abstract: A method includes determining one or more potential merges corresponding to a color set Ai and a color set Aj of N color sets, represented by A1 to AN, used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers from 1 to N, and i?j. One or more potential cuts corresponding to the color set Ai and the second color set Aj are determined. An index Aij is determined according to the one or more potential merges and the one or more potential cuts. A plurality of parameters F related to the index Aij is obtained based on various values of indices fi and fj. A parameter F is selected among the plurality of parameters F based on a definition of the index Aij.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pi-Tsung Chen, Ming-Hui Chih, Ken-Hsien Hsieh, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Wen-Ju Yang, Gwan Sin Chang, Yung-Sung Yen
  • Publication number: 20150008343
    Abstract: The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.
    Type: Application
    Filed: September 19, 2014
    Publication date: January 8, 2015
    Inventors: HUNG-CHUN WANG, PEI-SHIANG CHEN, TZU-CHIN LIN, FARUK KRECINIC, JENG-HORNG CHEN, WEN-CHUN HUANG, RU-GUN LIU
  • Patent number: 8850367
    Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a first plurality of features defined in a first layer and a second plurality of features defined in a second layer; converting the IC design layout to a topological diagram having nodes, chains and arrows; and identifying alignment conflict based on the topological diagram using rules associated with loop and path count.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ming Lai, Ken-Hsien Hsieh, Wen-Chun Huang, Ru-Gun Liu