Patents by Inventor Wen Chung

Wen Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230022210
    Abstract: Metal oxides-silica composite materials are synthesized by a co-precipitation method to serve as modified catalysts for converting ethanol into four-carbon hydrocarbons. The method includes mixing a liquid-phase silicon source and a metal precursor at different ratios so as to change the acid-base composition of the composite materials and thereby increase selectivity with respect to the four-carbon products.
    Type: Application
    Filed: September 16, 2022
    Publication date: January 26, 2023
    Inventors: Po-Wen CHUNG, Meng-Xun WU
  • Patent number: 11555531
    Abstract: A cycloid speed reducer includes an input shaft, a rolling assembly, first and second cycloid discs, a crankshaft and an output disc. The first and second cycloid discs are disposed around the input shaft and driven by the input shaft. The first and second cycloid discs are located at two opposite sides of the rolling assembly, respectively. The crankshaft includes first and second eccentric ends and first and second concentric ends integrally formed as a one-piece structure and arranged sequentially. The first and second eccentric ends are linked with the first and second cycloid discs respectively. An eccentricity value is between any neighboring two of the concentric and eccentric ends. The diameters of all the concentric and eccentric ends are equal. The output disc is linked with the first or second concentric end. The output disc is a power output end of the cycloid speed reducer.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: January 17, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chi-Wen Chung, Hung-Wei Lin, Wei-Ying Chu, Chin-Hsiang Chen
  • Publication number: 20230010037
    Abstract: A semiconductor structure includes two circuit regions and two inner seal rings, each of which surrounds one of the circuit regions. Each inner seal ring has a substantially rectangular periphery with four interior corner stress relief (CSR) structures. The semiconductor structure further includes an outer seal ring surrounding the two inner seal rings. The outer seal ring has a substantially rectangular periphery without CSR structures at four interior corners of the outer seal ring. The outer seal ring includes a plurality of first fin structures located between each of the two inner seal rings and a respective short side of the outer seal ring. Each first fin structure is parallel with the respective short side of the outer seal ring. Lengths of the first fin structures gradually decrease along a direction from the inner seal rings to the respective short side of the outer seal ring.
    Type: Application
    Filed: May 6, 2022
    Publication date: January 12, 2023
    Inventors: Shan-Yu Huang, Hsueh-Heng Lin, Shih-Chang Chen, Hsiao-Wen Chung, Yilun Chen
  • Publication number: 20220393003
    Abstract: A composite substrate is provided in some embodiments of the present disclosure, which includes a substrate, an insulation layer, a first silicon-containing layer and a first epitaxial layer. The insulation layer is disposed on the substrate. The first silicon-containing layer is disposed on the insulation layer, in which the first silicon-containing layer includes a plurality of group V atoms. The first epitaxial layer is disposed on the first silicon-containing layer, in which the first epitaxial layer includes a plurality of group III atoms. A distribution concentration of the group V atoms in the first silicon-containing layer increases as getting closer to the first epitaxial layer, and a distribution concentration of the group III atoms in the first epitaxial layer increases as getting closer to the first silicon-containing layer. A method of manufacturing a composite substrate is also provided in some embodiments of the present disclosure.
    Type: Application
    Filed: September 10, 2021
    Publication date: December 8, 2022
    Inventor: Wen-Chung LI
  • Patent number: 11511271
    Abstract: Metal oxides-silica composite materials are synthesized by a co-precipitation method to serve as modified catalysts for converting ethanol into four-carbon hydrocarbons. The method includes mixing a liquid-phase silicon source and a metal precursor at different ratios so as to change the acid-base composition of the composite materials and thereby increase selectivity with respect to the four-carbon products.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 29, 2022
    Assignee: ACADEMIA SINICA
    Inventors: Po-Wen Chung, Meng-Xun Wu
  • Publication number: 20220374623
    Abstract: An optical fingerprint identification structure is provided, including: a protective glass and an optical fingerprint identification module, wherein the optical fingerprint identification module is located under the protective glass. The protective glass of the present invention is of a thickness. The gap between the protective glass and the optical fingerprint identification module is an air gap. The optical fingerprint identification module further comprises: a receiving lens assembly, an image sensor module, a module housing, and a module housing extension, the receiving lens assembly is located at the top of the optical fingerprint identification module, that is, close to the air gap, and the image sensor module is located below the receiving lens assembly. As such, the size of the optical fingerprint identification structure is reduced, and is applicable to the side of device, so that the usable area on the front and back of the device is increased.
    Type: Application
    Filed: August 24, 2021
    Publication date: November 24, 2022
    Inventors: Hsu-Wen FU, Jun-Wen CHUNG, Yu-Heng CHEN, Yufan CHEN, Hung-Wen YANG
  • Publication number: 20220359271
    Abstract: A method of fabricating a semiconductor substrate includes the following steps. A carrier substrate is provided, and a plasma treatment is performed on the surface of the carrier substrate. A polycrystalline semiconductor layer is formed on the surface of the carrier substrate. A rapid thermal treatment is then performed on the polycrystalline semiconductor layer. A buried dielectric layer is then formed on the polycrystalline semiconductor layer. Afterwards, a single crystalline semiconductor layer is formed on the buried dielectric layer.
    Type: Application
    Filed: July 15, 2021
    Publication date: November 10, 2022
    Applicant: Wafer Works Corporation
    Inventors: Ping-Hai Chiao, Wen-Chung Li
  • Patent number: 11486469
    Abstract: A cycloid speed reducer includes an input shaft, a rolling assembly, a first cycloid disc, a second cycloid disc, a first crankshaft, a second crankshaft, a first output disc and a second output disc. The first cycloid disc and the second cycloid disc are disposed around the input shaft and rotated with the input shaft. The first cycloid disc and the second cycloid disc are located at two opposite sides of the rolling assembly, respectively. The first crankshaft includes a first concentric end and a first eccentric end. The first eccentric end is linked with the first cycloid disc. The second crankshaft includes a second concentric end and a second eccentric end. The second eccentric end is linked with the second cycloid disc. The first output disc is linked with the first concentric end. The second output disc is linked with the second concentric end.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: November 1, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chi-Wen Chung, Hung-Wei Lin
  • Publication number: 20220344225
    Abstract: A package comprises an interposer, comprising an interposer substrate including at least one layer, and a plurality of RDLs formed through at least a portion of the interposer substrate. The package also includes a die device structure comprising at least one device die, and a first test line (TL) structure interposed between the interposer and the die device structure. The first TL structure includes at least one first test line electrically coupled to the at least one device die, at least a portion of the at least one first test line extending beyond a peripheral edge of the die device structure to provide an electrical interface with the at least one device die.
    Type: Application
    Filed: September 8, 2021
    Publication date: October 27, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yang Hsieh, Chien-Chang Lee, Chia-Ping Lai, Wen-Chung Lu, Cheng-Kang Huang, Mei-Shih Kuo, Alice Huang
  • Publication number: 20220344280
    Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.
    Type: Application
    Filed: December 9, 2021
    Publication date: October 27, 2022
    Inventors: Tsung-Yang Hsieh, Chien-Chang Lee, Chia-Ping Lai, Wen-Chung Lu, Cheng-Kang Huang, Mei-Shih Kuo, Alice Huang
  • Publication number: 20220336621
    Abstract: Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wen Chung Yang, Shih Hsi Chen, Wei-Chang Lin
  • Publication number: 20220334167
    Abstract: A method for detecting defects in a GaN high electron mobility transistor is disclosed. The method includes steps of measuring a plurality of electrical characteristics of a GaN high electron mobility transistor, measuring the plurality of electrical characteristics after performing a deterioration test on the GaN high electron mobility transistor, irradiating the GaN high electron mobility transistor in turns with a plurality of light sources with different wavelengths and measuring the plurality of electrical characteristics after each irradiation of the GaN high electron mobility transistor by each of the plurality of light sources, and comparing changes of the plurality of electrical characteristics measured in the above steps to determine the defect location of the GaN high electron mobility transistor.
    Type: Application
    Filed: June 10, 2021
    Publication date: October 20, 2022
    Inventors: Ting-Chang CHANG, Hao-Xuan ZHENG, Yu-Shan LIN, Fu-Yuan JIN, Fong-Min CIOU, Mao-Chou TAI, Yun-Hsuan LIN, Wei-Chen HUANG, Wen-Chung CHEN
  • Publication number: 20220328685
    Abstract: A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Tseng Hsun Liu, Min-Hsuan Tsai, Ke-Feng Lin, Ming-Yen Liu, Wen-Chung Chang, Cherng-En Sun
  • Publication number: 20220310464
    Abstract: A semiconductor structure that includes two circuit regions; two inner seal rings, each of the two inner seal rings surrounding one of the two circuit regions; an outer seal ring surrounding the two inner seal rings, wherein each of the inner seal rings and the outer seal ring has a substantially rectangular periphery with four interior corner seal ring structures; four first redundant regions between the two inner seal rings and the outer seal ring, each of the four first redundant regions being a substantially trapezoidal shape; and first dummy patterns substantially uniformly distributed in the four first redundant regions.
    Type: Application
    Filed: June 2, 2021
    Publication date: September 29, 2022
    Inventors: Shan-Yu Huang, Hsiao-Wen Chung, Yi-Lun Chen, Huang-Sheng Lin
  • Patent number: 11453994
    Abstract: The present disclosure provides a work equipment system and a control method therefor. The work equipment system includes a work equipment, a temperature sensor and a controller. The work equipment includes a motor device, and the motor device is configured to provide a motive power to a load device. The temperature sensor is configured to measure a motor temperature. The controller is configured to: calculate a first current based on a required motive power command and electrical parameters; calculate a temperature difference between the motor temperature and a preset temperature; calculate a thermal power based on the temperature difference and a thermal resistance; calculate a second current based on the thermal power and the motor resistance; and compare the second current to an effective value of the first current for determining whether the second current is smaller than the first current.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: September 27, 2022
    Assignee: DELTA ELECTRONICS, INC
    Inventor: Chi-Wen Chung
  • Patent number: 11452191
    Abstract: A warning light control method includes the steps of: accepting multiple warning lights to receive a start command to set up Flash Mode and numbering each warning light sequentially starting from 1, and using Flash Mode number to synchronously set ID Number of each warning light; setting the ID Number of a predetermined warning light as Starter and the remaining ID Numbers as Receivers; the warning light of Starter receiving Start Command from Control Bus through cable, and sending Data, Clock Pulse and ID Information from Data Bus, and selecting one for flashing by Flash Mode; warning lights of Receivers get Data, Clock Pulse and ID Information from Data Bus through cables thereof, and warning lights of Receivers and Starter are flashing synchronously or asynchronously; whether Control Bus of Starter and Receivers has received Change ID Command.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: September 20, 2022
    Assignee: ESUSE AUTO PARTS MANUFACTURING CO., LTD.
    Inventors: Ting-Fang Lee, Wen-Chung Han
  • Publication number: 20220288448
    Abstract: A workout device includes a base frame, a top cover and a gliding mechanism. The base frame includes a chassis and through holes formed in the chassis. The top cover includes dome structures aligned with the through holes, respectively, when the top cover is assembled to the base frame. The gliding mechanism consists of multi-directional rotating members accommodated in the dome structures and partially protruding from the through holes, respectively, when the top cover is assembled to the base frame. In response to a pressing force exerted onto the cover body, the dome structures are in contact with the multi-directional rotating members so as to cause friction therebetween, and the friction changes with the force exerted onto the cover body.
    Type: Application
    Filed: February 22, 2022
    Publication date: September 15, 2022
    Inventor: WEN-CHUNG HSU
  • Patent number: 11434334
    Abstract: A composite material and a foam prepared from the composite material are provided. The composite material includes a network polymer, a fluorine-containing polymer fiber, and a reinforcement fiber. The polymer network is a crosslinking reaction product of a polymer and an oligomer, wherein the polymer is polyamide, polyester, polyurethane, or a combination thereof, and the oligomer is a vinyl aromatic-co-acrylate oligomer with an epoxy functional group. The oligomer has a weight percentage of 1% to 10%, based on the weight of the network polymer. The ratio of the weight of the reinforcement fiber to the total weight of the network polymer and the fluorine-containing polymer fiber is from 1:9 to 4:6.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: September 6, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shun Wen Cheng, Sheng-Lung Chang, Chin-Lang Wu, Ying-Chieh Chao, Shihn-Juh Liou, Wen-Chung Liang
  • Publication number: 20220272818
    Abstract: A warning light control method includes the steps of: accepting multiple warning lights to receive a start command to set up Flash Mode and numbering each warning light sequentially starting from 1, and using Flash Mode number to synchronously set ID Number of each warning light; setting the ID Number of a predetermined warning light as Starter and the remaining ID Numbers as Receivers; the warning light of Starter receiving Start Command from Control Bus through cable, and sending Data, Clock Pulse and ID Information from Data Bus, and selecting one for flashing by Flash Mode; warning lights of Receivers get Data, Clock Pulse and ID Information from Data Bus through cables thereof, and warning lights of Receivers and Starter are flashing synchronously or asynchronously; whether Control Bus of Starter and Receivers has received Change ID Command.
    Type: Application
    Filed: June 11, 2021
    Publication date: August 25, 2022
    Inventors: Ting-Fang LEE, Wen-Chung HAN
  • Publication number: 20220272819
    Abstract: Light device control circuit includes signal processor; control circuit including control signal source and active switch, active switch having output end thereof electrically connected to control input side of the signal processor through control bus; data synchronization circuit including data signal source and another set of active switches, and the output end of the another set of active switches being electrically connected to data input side of signal processor through data bus, signal processor forming electrical connection with signal connection circuit by data output side to form signal and command synchronization between data input side and data output side; and warning light control IC connected to warning lights and forming electrical connection with data bus outside data output side, and transmitting data, clock pulse and ID information from data output side, so that the starter and the receivers select one of the flash modes to flash the light.
    Type: Application
    Filed: March 15, 2022
    Publication date: August 25, 2022
    Inventors: Ting-Fang LEE, Wen-Chung HAN