Patents by Inventor Wen Fang

Wen Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130234141
    Abstract: A high voltage semiconductor device includes a substrate, an insulating layer positioned on the substrate, and a silicon layer positioned on the insulating layer. The silicon layer further includes at least a first doped strip, two terminal doped regions formed respectively at two opposite ends of the silicon layer and electrically connected to the first doped strip, and a plurality of second doped strips. The first doped strip and the terminal doped regions include a first conductivity type, the second doped strips include a second conductivity type, and the first conductivity type and the second conductivity type are complementary. The first doped strip and the second doped strips are alternately arranged.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Inventors: Pao-An Chang, Ching-Ming Lee, Te-Yuan Wu, Chih-Chung Wang, Wen-Fang Lee, Wei-Lun Hsu
  • Patent number: 8531166
    Abstract: The present invention discloses a constant on-time switching regulator, a control method therefor, and an on-time calculation circuit for calculating an on-time period of a constant on-time switching regulator. The on-time calculation circuit calculates on-time according to practical conditions. It includes: a driver gate receiving a gate signal of a power switch in a switching regulator, the driver gate operating between high and low levels of a first reference voltage and ground; a low pass filter receiving an output from the driver gate and generating a second reference voltage, a ratio between the second reference voltage and the first reference voltage being substantially the same as a duty ratio of the gate signal; and an on-time generator comparing the second reference voltage with a ramp signal to determine an on-time of the power switch.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: September 10, 2013
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Li-Wen Fang, Ting-Jung Tai, Chih-Hao Yang
  • Publication number: 20130221438
    Abstract: A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region includes a plurality of gaps formed therein. The non-continuous doped region further includes a second conductivity type complementary to the first conductivity type.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 29, 2013
    Inventors: Ming-Tsung Lee, Cheng-Hua Yang, Wen-Fang Lee, Chih-Chung Wang, Chih-Wei Hsu, Po-Ching Chuang
  • Publication number: 20130187225
    Abstract: A HV MOSFET device includes a substrate, a deep well region, a source/body region, a drain region, a gate structure, and a first doped region. The deep well region includes a boundary site and a middle site. The source/body region is formed in the deep well region and defines a channel region. The first doped region is formed in the deep well region and disposed under the gate structure, and having the first conductivity type. There is a first ratio between a dopant dose of the first doped region and a dopant dose of the boundary site of the deep well region. There is a second ratio between a dopant dose of the first doped region and a dopant dose of the middle site of the deep well region. A percentage difference between the first ratio and the second ratio is smaller than or equal to 5%.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 25, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chih-Chung WANG, Ming-Tsung Lee, Chung-I Huang, Shan-Shi Huang, Wen-Fang Lee, Te-Yuan Wu
  • Patent number: 8492835
    Abstract: A HV MOSFET device includes a substrate, a deep well region, a source/body region, a drain region, a gate structure, and a first doped region. The deep well region includes a boundary site and a middle site. The source/body region is formed in the deep well region and defines a channel region. The first doped region is formed in the deep well region and disposed under the gate structure, and having the first conductivity type. There is a first ratio between a dopant dose of the first doped region and a dopant dose of the boundary site of the deep well region. There is a second ratio between a dopant dose of the first doped region and a dopant dose of the middle site of the deep well region. A percentage difference between the first ratio and the second ratio is smaller than or equal to 5%.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: July 23, 2013
    Assignee: United Microelectronics Corporation
    Inventors: Chih-Chung Wang, Ming-Tsung Lee, Chung-I Huang, Shan-Shi Huang, Wen-Fang Lee, Te-Yuan Wu
  • Publication number: 20130173819
    Abstract: A stream condense unit coupled to a streaming server and a client player is provided. The stream condense unit includes a streaming data input unit, a stream content analysis unit, a frame timestamp adjust unit, and a streaming data output unit. The streaming data input unit is configured to receive a plurality of streaming content groups sent by the streaming server. The stream content analysis unit is configured to receive the plurality of streaming content groups, execute a content analysis to get importance scores of the source streaming contents. The frame timestamp adjust unit is configured to receive the condensed stream and adjust a timestamp of each frame in the condensed stream. The streaming data output unit is configured to receive the condensed stream and attach content identifying labels and tables to the condensed stream, and send the condensed stream to the client player to display.
    Type: Application
    Filed: September 10, 2012
    Publication date: July 4, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Hua Lee, Hui-Ping Kuo, Jen-Yu Yu, Wen-Fang Cheng
  • Publication number: 20130113049
    Abstract: The present invention discloses a fuse circuit for final test trimming of an integrated circuit (IC) chip. The fuse circuit includes at least one electrical fuse, at least one control switch corresponding to the electrical fuse, and a resistant device. The electrical fuse is connected with the control switch in series between a predetermined pin and a grounding pin. The control switch receives a control signal to determine whether a predetermined current flows through the corresponding electrical fuse and breaks the electrical fuse. The resistant device is coupled between a bulk terminal and a source terminal to increase a resistance of a parasitic channel, such that an electrostatic discharge (ESD) protection is enhanced, and errors of final test trimming of an IC chip are avoided.
    Type: Application
    Filed: January 25, 2012
    Publication date: May 9, 2013
    Inventors: LI-WEN FANG, Chih-Hao Yang, An-Tung Chen
  • Patent number: 8436418
    Abstract: The present invention provides a high-voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high-voltage well, a second doped region disposed in the high-voltage well, a first gate structure disposed on the high-voltage well between the second doped region and the first doped region, a doped channel region disposed in the high-voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high-voltage well. The high-voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: May 7, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chung Wang, Wei-Lun Hsu, Te-Yuan Wu, Ke-Feng Lin, Shan-Shi Huang, Ming-Tsung Lee, Wen-Fang Lee
  • Publication number: 20130111351
    Abstract: The present invention discloses a method for remotely controlling a mobile terminal and a mobile terminal, wherein the method comprises: receiving, by a first mobile terminal, a touch-screen operation to an interface to be controlled, wherein the interface to be controlled is sent by a second mobile terminal during a video call, and acquiring a first touch-screen coordinate of the operation; converting, by the first mobile terminal, the first touch-screen coordinate into an interface coordinate of the interface to be controlled; and sending, by the first mobile terminal, the interface coordinate to the second mobile terminal to control the interface to be controlled.
    Type: Application
    Filed: November 12, 2010
    Publication date: May 2, 2013
    Applicant: ZTE CORPORATION
    Inventors: Lianfang Huang, Yang Liu, Wen Fang
  • Publication number: 20120319189
    Abstract: The present invention provides a high-voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high-voltage well, a second doped region disposed in the high-voltage well, a first gate structure disposed on the high-voltage well between the second doped region and the first doped region, a doped channel region disposed in the high-voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high-voltage well. The high-voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 20, 2012
    Inventors: Chih-Chung Wang, Wei-Lun Hsu, Te-Yuan Wu, Ke-Feng Lin, Shan-Shi Huang, Ming-Tsung Lee, Wen-Fang Lee
  • Publication number: 20120313175
    Abstract: The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 13, 2012
    Inventors: Chih-Chung Wang, Wei-Lun Hsu, Te-Yuan Wu, Wen-Fang Lee, Ke-Feng Lin, Shan-Shi Huang, Ming-Tsung Lee
  • Publication number: 20120309352
    Abstract: A system, method, and apparatus for establishing communications with a secure network using a non-secure mobile device operating in a non-secure network are disclosed herein. The disclosed method involves communicating a mobile device identifier to the secure network. In one or more embodiments, the mobile device identifier is an Internet protocol (IP) address and/or a unique identification (ID) code. The method further involves verifying and/or validating, with a mobile device manager in the secure network, the mobile device identifier. Also, the method involves establishing a secure connection between the mobile device and the secure network. In addition, the method involves receiving, with the mobile device, encrypted secure data from the secure network. Further, the method involves decrypting, with the mobile device, the received encrypted secure data using previously downloaded mobile device security software.
    Type: Application
    Filed: June 3, 2011
    Publication date: December 6, 2012
    Applicant: THE BOEING COMPANY
    Inventor: Wen Fang
  • Patent number: 8318411
    Abstract: Method for fabricating an interposer is provided. A substrate is provided having thereon at least a conductive via and at least a flange. The flange is bonded on the substrate and shades a portion of the via. A photoresist layer is formed on the interior surface of the via, on a contact surface of the flange and on an inner surface of the flange opposite to the contact surface. An opening is formed in the photoresist layer to expose a portion of the contact surface of the flange, while the photoresist layer still covers the interior surface of the via and the inner surface of the flange. A plating layer is formed on the exposed contact surface of the flange. The photoresist layer is then removed.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: November 27, 2012
    Assignee: Unimicron Technology Corp.
    Inventors: Chang-Ming Lee, Wen-Fang Liu, Shih-Jung Huang, Ling-Kai Su
  • Patent number: 8313724
    Abstract: In some embodiments, the present invention relates to new processes to simultaneously shorten and functionalize raw or purified carbon nanotubes to improve their dispersity and processibility, and the short functionalized nanotubes that may be made by the processes. This present invention also relates to new compositions of matter using short functionalized carbon nanotubes with thermoset, thermoplastic polymers, high temperature polymers, and other materials; the processes for making such composite materials; and the products of said processes.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: November 20, 2012
    Assignee: William Marsh Rice University
    Inventors: Wen-Fang Hwang, Zheyl Chen, James M. Tour
  • Publication number: 20120276650
    Abstract: A method for determining a turbidity point and a free carbohydrate buffer coefficient of an iron-carbohydrate complex. The method includes: (1) contacting the complex with an acid; (2) determining hydrogen ion concentrations and solution turbidities of the complex in acid degradation; and (3) mathematically fitting the data, to obtain the turbidity point of the complex and the free carbohydrate buffer coefficient through mathematical treatment. A method for evaluating the safety of the iron-carbohydrate complex with the turbidity point and the free carbohydrate buffer coefficient.
    Type: Application
    Filed: January 13, 2010
    Publication date: November 1, 2012
    Applicant: NANJING LIFENERGY R&D CO., LTD.
    Inventors: Wen Fang, Chuanzheng Hua, Jie Yang, Guoxin He, Shoujun Xiong
  • Patent number: 8294042
    Abstract: A method of manufacturing a connector is provided. Firstly, a substrate having a first surface, a second surface opposite to the first surface and a through hole is provided. Next, a first conductive layer covering the inside wall of the through hole is formed on the substrate. Then, a filler is filled in the through hole to form a filler post. Next, a conductive elastic cantilever is formed over the first surface and electrically connected to the first conductive layer. Then, a gold layer is formed on the conductive elastic cantilever and over the first surface. A solder ball electrically connected to the first conductive layer is formed over the second surface.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: October 23, 2012
    Assignee: Unimicron Technology Corp.
    Inventors: Chang-Ming Lee, Wen-Fang Liu, Shih-Jung Huang, Ling-Kai Su
  • Patent number: 8288662
    Abstract: A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: October 16, 2012
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Chang-Ming Lee, Wen-Fang Liu, Cheng-Po Yu
  • Patent number: 8274798
    Abstract: A carrier substrate includes a substrate having a chip side and a PCB side, a plurality of bond pads disposed on the chip side for bonding a chip, a plurality of land grid array (LGA) pads disposed on the PCB side, and a plurality of resilient flanges installed on the PCB side in an array manner. The plurality of resilient flanges electrically connects with the LGA pads correspondingly.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: September 25, 2012
    Assignee: Unimicron Technology Corp.
    Inventors: Shih-Jung Huang, Wen-Fang Liu, Ling-Kai Su
  • Publication number: 20120236104
    Abstract: The present invention discloses a method for user position notification and a mobile terminal thereof. The mobile terminal includes: an acquisition module configured for acquiring videophone images and mobile terminal position information; a transmitter module configured for concurrently transmitting the video phone images and position information to the call opposite end of the mobile terminal. The present invention enables the user to acquire the position and video images of the opposite end at the same time, and therefore improves satisfaction of the user.
    Type: Application
    Filed: September 9, 2010
    Publication date: September 20, 2012
    Applicant: ZTE CORPORATION
    Inventors: Wen Fang, Yang Liu
  • Patent number: 8247705
    Abstract: A manufacturing method of a circuit substrate includes the following steps. A dielectric layer is formed on at least one surface of a substrate. An insulating layer is formed on the dielectric layer. A portion of the insulating layer and a portion of the dielectric layer are removed, so as to form at least one blind via in the dielectric layer and the insulating layer. An electroless plating layer is formed on the sidewall of the blind via and a remaining portion of the insulating layer, wherein the binding strength between the insulating layer and the electroless plating layer is greater than that between the dielectric layer and the electroless plating layer. A patterned conductive layer is plated to cover the electroless plating layer.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: August 21, 2012
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Chang-Ming Lee, Wen-Fang Liu, Cheng-Po Yu