Patents by Inventor Wen-hao Cheng
Wen-hao Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12176253Abstract: A deposition system provides a feature that may reduce costs of the sputtering process by increasing a target change interval. The deposition system provides an array of magnet members which generate a magnetic field and redirect the magnetic field based on target thickness measurement data. To adjust or redirect the magnetic field, at least one of the magnet members in the array tilts to focus on an area of the target where more target material remains than other areas. As a result, more ion, e.g., argon ion bombardment occurs on the area, creating more uniform erosion on the target surface.Type: GrantFiled: June 26, 2023Date of Patent: December 24, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Hao Cheng, Hsuan-Chih Chu, Yen-Yu Chen, Yi-Ming Dai
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Patent number: 12164221Abstract: An EUV reflective structure includes a substrate and multiple pairs of a Si layer and a Mo layer. The Si layer includes a plurality of cavities.Type: GrantFiled: July 28, 2023Date of Patent: December 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Benny Ku, Keith Kuang-Kuo Koai, Wen-Hao Cheng
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Publication number: 20240392430Abstract: A deposition system is provided capable of cleaning itself by removing a target material deposited on a surface of a collimator. The deposition system in accordance with the present disclosure includes a substrate process chamber. The deposition includes a substrate pedestal in the substrate process chamber, the substrate pedestal configured to support a substrate, a target enclosing the substrate process chamber, and a collimator having a plurality of hollow structures disposed between the target and the substrate, a vibration generating unit, and cleaning gas outlet.Type: ApplicationFiled: July 30, 2024Publication date: November 28, 2024Inventors: Wen-Hao CHENG, Hsuan-Chih CHU, Yen-Yu CHEN
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Publication number: 20240384417Abstract: A thin film deposition system includes: a first precursor supply system configured to generate and supply a first precursor vapor from a first precursor source, the first precursor supply system comprising a first precursor source container, wherein at least a portion of an interior surface of the first precursor source container has a three-dimensional (3D) pattern, wherein the 3D pattern comprises a plurality of area enlarging elements configured to enlarge a total contact area of the interior surface of the first precursor source container with the first precursor source stored therein; and a deposition chamber in gas communication with the first precursor source container, the deposition chamber configured to receive the first precursor vapor and deposit a layer of a first precursor source onto a substrate placed in the deposition chamber.Type: ApplicationFiled: July 30, 2024Publication date: November 21, 2024Inventors: Wen-Hao Cheng, Hsuan-Chih Chu, Yen-Yu Chen
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Publication number: 20240387156Abstract: A deposition system is provided capable of controlling an amount of a target material deposited on a substrate and/or direction of the target material that is deposited on the substrate. The deposition system in accordance with the present disclosure includes a substrate process chamber. The deposition includes a substrate pedestal in the substrate process chamber, the substrate pedestal configured to support a substrate, a target enclosing the substrate process chamber, and a collimator having a plurality of hollow structures disposed between the target and the substrate, wherein a length of at least one of the plurality of hollow structures is adjustable.Type: ApplicationFiled: July 30, 2024Publication date: November 21, 2024Inventors: Wen-Hao CHENG, Hsuan-Chih CHU, Yen-Yu CHEN
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Publication number: 20240389482Abstract: A resistive memory cell includes a lower electrode, a resistive transition metal oxide layer, and an upper electrode. The lower electrode includes at least one lower metallic barrier layer, a lower metal layer including a first metal having a melting point higher than 2,000 degrees Celsius, and a transition metal compound layer including an oxide or nitride of a transition metal selected from Ti, Ta, and W. The resistive transition metal oxide layer includes a conductive-filament-forming dielectric oxide of at least one transition metal and located on the transition metal compound layer. The upper electrode includes an upper metal layer including a second metal having a melting point higher than 2,000 degrees Celsius and at least one upper metallic barrier layer.Type: ApplicationFiled: July 21, 2024Publication date: November 21, 2024Inventors: Wen-Hao CHENG, Yuan-Huang LEE, Yu-Wen LIAO, Yen-Yu CHEN, Hsuan-Chih CHU
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Publication number: 20240381787Abstract: A sputtering target structure includes a back plate characterized by a first size and a plurality of sub-targets bonded to the back plate. Each of the sub-targets is characterized by a size that is a fraction of the first size and is no greater than a threshold target size. A given sub-target characterized by a size no greater than the threshold target size exhibits no crack formation in a sputtering operation. Each of the plurality of sub-targets is in direct contact with one or more adjacent sub targets.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Inventors: Wen-Hao Cheng, Hsuan-Chih Chu, Yen-Yu Chen
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Publication number: 20240337949Abstract: A lithography exposure system includes a light source, a substrate stage, and a mask stage between the light source and the substrate stage along an optical path from the light source to the substrate stage. The lithography exposure system further comprises a reflector along the optical path. The reflector comprises: a first layer having a first material and a first thickness; a second layer having the first material and a second thickness different from the first thickness; and a third layer between the first layer and the second layer, and having a second material different from the first material.Type: ApplicationFiled: June 18, 2024Publication date: October 10, 2024Inventors: Eng Hock LEE, Wen-Hao CHENG
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Publication number: 20240321613Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.Type: ApplicationFiled: May 30, 2024Publication date: September 26, 2024Inventors: Peng-Ren Chen, Wen-Hao Cheng, Jyun-Hong Chen, Chien-Hui Chen
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Publication number: 20240312939Abstract: A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.Type: ApplicationFiled: May 27, 2024Publication date: September 19, 2024Inventors: MING-HO TSAI, JYUN-HONG CHEN, CHUN-CHEN LIU, YU-NU HSU, PENG-REN CHEN, WEN-HAO CHENG, CHI-MING TSAI
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Patent number: 12089506Abstract: A sputtering target structure includes a back plate characterized by a first size, and a plurality of sub-targets bonded to the back plate. Each of the sub-targets is characterized by a size that is a fraction of the first size and is equal to or less than a threshold target size. Each sub-target includes a ferromagnetic material containing iron (Fe) and boron (B). Each of the plurality of sub-targets is in direct contact with one or more adjacent sub-targets.Type: GrantFiled: January 18, 2022Date of Patent: September 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Hao Cheng, Hsuan-Chih Chu, Yen-Yu Chen
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Publication number: 20240271314Abstract: The present disclosure is directed to a fluid head that is configured to eject a first fluid (e.g., a liquid state fluid) and a second fluid (e.g., a gaseous state fluid). The fluid head is movable in a rotatable-fashion and a translatable-fashion such that the fluid head may be utilized to increase a speed and decrease a period of time for cleaning and drying a workpiece after an electro-chemical polishing (ECP) process or step. The fluid head may also be utilized to increase a speed and decrease a period of time for beveling an edge of a conductive layer on the workpiece. The present disclosure is also directed to methods for cleaning and drying the workpiece as well as beveling the conductive layer of the workpiece utilizing the fluid head.Type: ApplicationFiled: February 10, 2023Publication date: August 15, 2024Inventors: Wen-Hao CHENG, Hsuan-Chih CHU, Yen-Yu CHEN, Zong-Kun LIN
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Publication number: 20240258142Abstract: A device includes a movable blade having a first surface to receive a semiconductor wafer. The device can include a positional sensor to detect a position of the semiconductor wafer on a surface of the movable blade, relative to a stationary body. The movable blade can be configured to move relative to the stationary body to cause a displacement of the semiconductor wafer relative to the movable blade. The positional sensor can be coupled to the movable blade.Type: ApplicationFiled: January 31, 2023Publication date: August 1, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Hao Cheng, Hsuan-Chih Chu, Yen-Yu Chen
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Patent number: 12050405Abstract: A lithography exposure system includes a light source, a substrate stage, and a mask stage between the light source and the substrate stage along an optical path from the light source to the substrate stage. The lithography exposure system further comprises a reflector along the optical path. The reflector comprises: a first layer having a first material and a first thickness; a second layer having the first material and a second thickness different from the first thickness; and a third layer between the first layer and the second layer, and having a second material different from the first material.Type: GrantFiled: August 10, 2022Date of Patent: July 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Eng Hock Lee, Wen-Hao Cheng
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Patent number: 12040293Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.Type: GrantFiled: November 14, 2022Date of Patent: July 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
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Patent number: 12030008Abstract: A device for removing particles in a gas stream includes a first cylindrical portion configured to receive the gas stream containing a target gas and the particles, a rotatable device disposed within the first cylindrical portion and configured to generate a centrifugal force when in a rotational action to divert the particles away from the rotatable device, a second cylindrical portion coupled to the first cylindrical portion and configured to receive the target gas, and a third cylindrical portion coupled to the first cylindrical portion and surrounding the second cylindrical portion, the third cylindrical portion being configured to receive the diverted particles.Type: GrantFiled: July 28, 2021Date of Patent: July 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Hao Cheng, Hsuan-Chih Chu, Yen-Yu Chen
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Patent number: 12033965Abstract: A method is provided. The method includes forming an interconnect structure electrically connected to a semiconductor device; forming a tantalum-based barrier layer over the interconnect structure; oxidizing the tantalum-based barrier layer to form a tantalum oxide over the tantalum-based barrier layer; and forming a metal layer over the tantalum oxide.Type: GrantFiled: May 4, 2023Date of Patent: July 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Hao Cheng, Yen-Yu Chen, Chih-Wei Lin, Yi-Ming Dai
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Patent number: 12027396Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.Type: GrantFiled: February 2, 2023Date of Patent: July 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Peng-Ren Chen, Wen-Hao Cheng, Jyun-Hong Chen, Chien-Hui Chen
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Patent number: 12021050Abstract: A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.Type: GrantFiled: July 26, 2022Date of Patent: June 25, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Ho Tsai, Jyun-Hong Chen, Chun-Chen Liu, Yu-Nu Hsu, Peng-Ren Chen, Wen-Hao Cheng, Chi-Ming Tsai
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Publication number: 20240201435Abstract: The present disclosure provides an embodiment of a photonics structure that includes a ring optical waveguide on a substrate; a rail optical waveguide configured to couple a light into the ring optical waveguide; and enhancement features configured around the ring optical waveguide and the rail optical waveguide to enhancement the photonic structure.Type: ApplicationFiled: May 26, 2023Publication date: June 20, 2024Inventor: Wen-Hao Cheng