Patents by Inventor Wen-Hsin Lin
Wen-Hsin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9666711Abstract: A semiconductor device is provided. The semiconductor device includes a first conductive type substrate; a second conductive type body region disposed in the first conductive type substrate, wherein the first conductive type is different from the second conductive type; a first conductive type first well region disposed in the second conductive type body region; a gate structure disposed over the top surface of the first conductive type substrate; a source region, wherein the source region includes a heavily-doped first conductive type source region and is disposed in the second conductive type body region; and a drain region, wherein the drain region is heavily doped first conductive type and is disposed in the first conductive type first well region.Type: GrantFiled: May 31, 2016Date of Patent: May 30, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Wen-Hsin Lin, Shin-Cheng Lin
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Publication number: 20170092755Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.Type: ApplicationFiled: December 13, 2016Publication date: March 30, 2017Inventors: Shang-Hui TU, Chih-Jen HUANG, Jui-Chun CHANG, Shin-Cheng LIN, Yu-Hao HO, Wen-Hsin LIN
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Publication number: 20170054369Abstract: A switch-mode converter includes a high-side driver, a high-side transistor, a low-side driver, a low-side transistor, a capacitor, and an active diode. The high-side driver is supplied by the bootstrap voltage of the bootstrap node and a floating reference voltage of a floating reference node, and generates the high-side output signal. The high-side transistor provides an input voltage to the floating reference node according to the high-side output signal. The low-side driver generates the low-side output signal. The low-side transistor couples the floating reference node to a ground according to the low-side output signal. The capacitor is coupled between the bootstrap node and the floating reference node. The active diode provides the supply voltage to the bootstrap node. When the bootstrap voltage exceeds the supply voltage, the active diode isolates the supply voltage from the bootstrap node.Type: ApplicationFiled: December 2, 2015Publication date: February 23, 2017Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Yu-Lung CHIN, Shin-Cheng LIN, Wen-Hsin LIN, Yu-Hao HO
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Publication number: 20170054357Abstract: A high-side circuit, adapted for a switched-mode converter, includes a level shifter, a high-side driver, a high-side transistor, a capacitor, and an active diode. The level shifter receives a first signal to generate a set signal. The high-side driver is supplied by a bootstrap voltage of a bootstrap node and a floating reference voltage of a floating reference node, which controls the high-side transistor to provide an input voltage to the floating reference node according to the set signal. The capacitor is coupled between the bootstrap node and the floating reference node. The active diode provides a supply voltage to the bootstrap node. When the bootstrap voltage exceeds the supply voltage, the active diode isolates the supply voltage from the bootstrap node according to a control voltage. The active diode includes a first-type well coupled to the bootstrap node, where the high-side driver is disposed.Type: ApplicationFiled: December 28, 2015Publication date: February 23, 2017Applicant: Vanguard International Semiconductor CorporationInventors: Yu-Lung CHIN, Shin-Cheng LIN, Wen-Hsin LIN, Yu-Hao HO
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Patent number: 9577506Abstract: A high-side circuit, adapted for a switched-mode converter, includes a level shifter, a high-side driver, a high-side transistor, a capacitor, and an active diode. The level shifter receives a first signal to generate a set signal. The high-side driver is supplied by a bootstrap voltage of a bootstrap node and a floating reference voltage of a floating reference node, which controls the high-side transistor to provide an input voltage to the floating reference node according to the set signal. The capacitor is coupled between the bootstrap node and the floating reference node. The active diode provides a supply voltage to the bootstrap node. When the bootstrap voltage exceeds the supply voltage, the active diode isolates the supply voltage from the bootstrap node according to a control voltage. The active diode includes a first-type well coupled to the bootstrap node, where the high-side driver is disposed.Type: GrantFiled: December 28, 2015Date of Patent: February 21, 2017Assignee: Vanguard International Semiconductor CorporationInventors: Yu-Lung Chin, Shin-Cheng Lin, Wen-Hsin Lin, Yu-Hao Ho
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Patent number: 9559200Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.Type: GrantFiled: February 24, 2016Date of Patent: January 31, 2017Assignee: Vanguard International Semiconductor CorporationInventors: Shang-Hui Tu, Chih-Jen Huang, Jui-Chun Chang, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin
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Patent number: 9455345Abstract: A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.Type: GrantFiled: January 27, 2016Date of Patent: September 27, 2016Assignee: Vanguard International Semiconductor CorporationInventors: Shin-Cheng Lin, Shang-Hui Tu, Yu-Hao Ho, Wen-Hsin Lin
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Publication number: 20160172487Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.Type: ApplicationFiled: February 24, 2016Publication date: June 16, 2016Inventors: Shang-Hui TU, Chih-Jen HUANG, Jui-Chun CHANG, Shin-Cheng LIN, Yu-Hao HO, Wen-Hsin LIN
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Publication number: 20160141414Abstract: A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.Type: ApplicationFiled: January 27, 2016Publication date: May 19, 2016Inventors: Shin-Cheng LIN, Shang-Hui TU, Yu-Hao HO, Wen-Hsin LIN
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Patent number: 9306034Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.Type: GrantFiled: February 24, 2014Date of Patent: April 5, 2016Assignee: Vanguard International Semiconductor CorporationInventors: Shang-Hui Tu, Chih-Jen Huang, Jui-Chun Chang, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin
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Patent number: 9299528Abstract: A method for manufacturing a printed circuit board is disclosed, which comprises the following steps. A basic board having an upper surface and a bottom surface opposite to the upper surface is provided. A plurality of the electronic components temporarily disposed on the basic board is provided. At least one locating pin temporarily disposed on a place of the basic board is provided, in which the electronic components are not temporarily disposed on the place. Surface mount technology is used simultaneously to joint at least one locating pin and the electronic components on the basic board.Type: GrantFiled: June 15, 2012Date of Patent: March 29, 2016Assignee: AU OPTRONICS CORPORATIONInventors: Wen-Hsin Lin, Ching-Kun Lai, Chien-Hung Chen
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Patent number: 9269808Abstract: A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.Type: GrantFiled: February 21, 2014Date of Patent: February 23, 2016Assignee: Vanguard International Semiconductor CorporationInventors: Shin-Cheng Lin, Shang-Hui Tu, Yu-Hao Ho, Wen-Hsin Lin
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Publication number: 20150279986Abstract: The present disclosure provides a semiconductor device, including a semiconductor substrate, an epitaxial structure, a well region, a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. At least one set of first, second and third heavily doped regions formed in the well region between source and drain regions, wherein the first, second and third heavily doped regions are adjoined sequentially from bottom to top. A gate structure disposed over the epitaxial structure. The present disclosure also provides a method for manufacturing the semiconductor device.Type: ApplicationFiled: April 21, 2015Publication date: October 1, 2015Applicant: Vanguard International Semiconductor CorporationInventors: Shang-Hui TU, Chih-Jen HUANG, Jui-Chun CHANG, Yu-Hao HO, Wen-Hsin LIN, Shin-Cheng LIN
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Patent number: 9129989Abstract: The present disclosure provides a semiconductor device, including a semiconductor substrate, an epitaxial structure, a well region, a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. At least one set of first, second and third heavily doped regions formed in the well region between source and drain regions, wherein the first, second and third heavily doped regions are adjoined sequentially from bottom to top. A gate structure disposed over the epitaxial structure. The present disclosure also provides a method for manufacturing the semiconductor device.Type: GrantFiled: April 21, 2015Date of Patent: September 8, 2015Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Shang-Hui Tu, Chih-Jen Huang, Jui-Chun Chang, Yu-Hao Ho, Wen-Hsin Lin, Shin-Cheng Lin
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Publication number: 20150243780Abstract: A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.Type: ApplicationFiled: February 21, 2014Publication date: August 27, 2015Applicant: Vanguard International Semiconductor CorporationInventors: Shin-Cheng LIN, Shang-Hui TU, Yu-Hao HO, Wen-Hsin LIN
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Publication number: 20150243766Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.Type: ApplicationFiled: February 24, 2014Publication date: August 27, 2015Applicant: Vanguard International Semiconductor CorporationInventors: Shang-Hui TU, Chih-Jen HUANG, Jui-Chun CHANG, Shin-Cheng LIN, Yu-Hao HO, Wen-Hsin LIN
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Patent number: 9054129Abstract: The present disclosure provides a semiconductor device, including a semiconductor substrate, an epitaxial structure, a well region, a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. At least one set of first, second and third heavily doped regions formed in the well region between source and drain regions, wherein the first, second and third heavily doped regions are adjoined sequentially from bottom to top. A gate structure disposed over the epitaxial structure. The present disclosure also provides a method for manufacturing the semiconductor device.Type: GrantFiled: March 26, 2014Date of Patent: June 9, 2015Assignee: Vanguard International Semiconductor CorporationInventors: Shang-Hui Tu, Chih-Jen Huang, Jui-Chun Chang, Yu-Hao Ho, Wen-Hsin Lin, Shin-Cheng Lin
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Publication number: 20140367841Abstract: The present disclosure relates to a semiconductor package structure and semiconductor process. The semiconductor package includes a first substrate, a second substrate, a die, a plurality of interconnection elements and an encapsulation material. Each of the interconnection elements connects the first substrate and the second substrate. The encapsulation material encapsulates the interconnection elements. The encapsulation material defines a plurality of accommodation spaces to accommodate the interconnection elements, and the profile of each accommodation space is defined by the individual interconnection element, whereby the warpage behavior of the first substrate is in compliance with that of the second substrate during reflow.Type: ApplicationFiled: June 12, 2014Publication date: December 18, 2014Inventors: Shih-Ming HUANG, Chun-Hung LIN, Yi-Ting CHEN, Wen-Hsin LIN, Shih-Wei CHAN, Yung-Hsing CHANG
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Publication number: 20140193384Abstract: A method for liver protection of a mammal is provided and includes administering an effective amount of isolated Lactobacillus plantarum CMU995 thereto. Providing a new use of Lactobacillus plantarum CMU995, which is deposited at the Food Industry Research and Development Institute (FIRDI) in Taiwan under accession number BCRC 910472 and in the German Collection of Microorganisms and Cell Cultures (DSMZ) under accession number DSM 23780.Type: ApplicationFiled: March 12, 2014Publication date: July 10, 2014Applicant: China Medical UniversityInventors: Wen-Hsin LIN, Chi-Rei WU
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Patent number: 8709784Abstract: A method for liver protection of a mammal is provided and includes administering an effective amount of isolated Lactobacillus plantarum CMU995 thereto. Providing a new use of Lactobacillus plantarum CMU995, which is deposited at the Food Industry Research and Development Institute (FIRDI) in Taiwan under accession number BCRC 910472 and in the German Collection of Microorganisms and Cell Cultures (DSMZ) under accession number DSM 23780.Type: GrantFiled: January 8, 2013Date of Patent: April 29, 2014Assignee: China Medical UniversityInventors: Wen-Hsin Lin, Chi-Rei Wu