Patents by Inventor Wen-Hsing Hsieh
Wen-Hsing Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9276114Abstract: Disclosed are a method to fabricate a semiconductor device having a two-layered gate structure, and so fabricated a semiconductor. The gate threshold voltage can be tuned by using two metal layers with different workfunctions, disposed over a fin structure on a substrate and extending in parallel to the current flow direction in the fin structure, and by varying individual thicknesses of the layer so as to change the relative coverage of the fin structure by the layers. The method may comprise providing a substrate having a fin structure, depositing first and second gate metals, and forming a gate dielectric layer. The method may further comprise determining the workfunctions of the first and second gate metals and their thicknesses to achieve a desired gate threshold voltage. Forming the first and second gate metal layers and the dielectric layer may use processes such as deposition, epitaxial growth, CMP, or selective etching.Type: GrantFiled: February 1, 2013Date of Patent: March 1, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jean-Pierre Colinge, Wen-Hsing Hsieh
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Publication number: 20160005660Abstract: Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.Type: ApplicationFiled: July 6, 2015Publication date: January 7, 2016Inventors: Hsueh-Shih Fan, Sun-Jay Chang, Chia-Hsin Hu, Min-Chang Liang, Shien-Yang Wu, Wen-Hsing Hsieh, Ching-Fang Huang
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Patent number: 9230828Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.Type: GrantFiled: August 12, 2014Date of Patent: January 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang Wu, Wen-Hsing Hsieh, Hua Feng Chen, Ting-Yun Wu, Carlos H. Diaz, Tzer-Min Shen, Ya-Yun Cheng
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Publication number: 20150372083Abstract: A semiconductor device includes a substrate, a first source/drain (S/D) region, a second S/D region, and a semiconductor sheet. The first S/D region is disposed on the substrate. The second S/D region is disposed above the first S/D region. The semiconductor sheet interconnects the first and second S/D regions and includes a plurality of turns. A method for fabricating the semiconductor device is also disclosed.Type: ApplicationFiled: December 2, 2014Publication date: December 24, 2015Inventors: HAO-LING TANG, JON-HSU HO, SHAO-HWANG SIA, WEN-HSING HSIEH, CHING-WEI TSAI
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Patent number: 9219152Abstract: A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs.Type: GrantFiled: October 23, 2012Date of Patent: December 22, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang Wu, Jeffrey Junhao Xu, Chih-Hao Chang, Wen-Hsing Hsieh
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Patent number: 9147753Abstract: An embodiment fin field effect transistor (FinFET) device and method of forming the same. An embodiment method of forming a fin field effect transistor (FinFET) includes forming fins from a semiconductor substrate, forming a field oxide between the fins, forming a sacrificial gate over a channel region of the fins projecting from the field oxide, and implanting ions through the sacrificial gate to provide the channel region of the fins with a uniform doping profile.Type: GrantFiled: November 21, 2012Date of Patent: September 29, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jean-Pierre Colinge, Wen-Hsing Hsieh
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Patent number: 9093566Abstract: Disclosed are a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.Type: GrantFiled: July 25, 2013Date of Patent: July 28, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Shih Fan, Sun-Jay Chang, Chia-Hsin Hu, Min-Chang Liang, Shien-Yang Wu, Wen-Hsing Hsieh, Ching-Fang Huang
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Publication number: 20150162334Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.Type: ApplicationFiled: February 18, 2015Publication date: June 11, 2015Inventors: Jon-Hsu HO, Chih-Ching WANG, Ching-Fang HUANG, Wen-Hsing HSIEH, Tsung-Hsing YU, Yi-Ming SHEU, Chih-Chieh YEH, Ken-Ichi GOTO, Zhiqiang WU
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Patent number: 8987824Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.Type: GrantFiled: November 22, 2011Date of Patent: March 24, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Chih-Chieh Yeh, Ken-Ichi Goto, Zhiqiang Wu
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Publication number: 20150079752Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.Type: ApplicationFiled: November 13, 2014Publication date: March 19, 2015Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
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Patent number: 8981479Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.Type: GrantFiled: December 17, 2013Date of Patent: March 17, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ching Wang, Jon-Hsu Ho, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Ken-Ichi Goto, Zhiqiang Wu
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Publication number: 20140349458Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.Type: ApplicationFiled: August 12, 2014Publication date: November 27, 2014Inventors: Zhiqiang Wu, Wen-Hsing Hsieh, Hua Feng Chen, Ting-Yun Wu, Carlos H. Diaz, Tzer-Min Shen, Ya-Yun Cheng
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Patent number: 8890207Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.Type: GrantFiled: December 22, 2011Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
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Patent number: 8866235Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.Type: GrantFiled: November 9, 2012Date of Patent: October 21, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang Wu, Wen-Hsing Hsieh, Hua Feng Chen, Ting-Yun Wu, Carlos H. Diaz, Ya-Yun Cheng, Tzer-Min Shen
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Publication number: 20140264493Abstract: A semiconductor device includes a substrate, a gate stack having at least one gate vertex directed to an area in the substrate below the gate stack. The semiconductor device also includes a source structure having at least one vertex directed toward the area in the substrate and a drain structure having at least one vertex directed toward the area in the substrate.Type: ApplicationFiled: April 26, 2013Publication date: September 18, 2014Inventors: Yu-Hung Cheng, Ching-Wei Tsai, Wen-Hsing Hsieh, Cheng-Ta Wu, Yeur-Luen Tu
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Patent number: 8836018Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device precursor. The semiconductor device precursor includes a substrate, source/drain regions on the substrate, dummy gate stacks separating the source/drain regions on the substrate and a doped region under the dummy gate stacks. The dummy gate stack is removed to form a gate trench. The doped region in the gate trench is recessed to form a channel trench. A channel layer is deposited in the channel trench to form a channel region and then a high-k (HK) dielectric layer and a metal gate (MG) are deposited on the channel region.Type: GrantFiled: November 16, 2012Date of Patent: September 16, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chieh Yang, Wei-Hao Wu, Wen-Hsing Hsieh, Zhiqiang Wu
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Publication number: 20140183641Abstract: Disclosed are a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.Type: ApplicationFiled: July 25, 2013Publication date: July 3, 2014Applicant: Taiwan Semiconductor Manufacturing Comapny, Ltd.Inventors: Hsueh-Shih Fan, Sun-Jay Chang, Chia-Hsin Hu, Min-Chang Liang, Shien-Yang Wu, Wen-Hsing Hsieh, Ching-Fang Huang
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Patent number: 8765533Abstract: A FinFET device and method for fabricating a FinFET device are disclosed. An exemplary method includes providing a substrate; forming a fin over the substrate; forming an isolation feature over substrate; forming a gate structure including a dummy gate over a portion of the fin, the gate structure traversing the fin, wherein the gate structure separates a source region and a drain region of the fin, a channel being defined in the portion of the fin between the source region and the drain region; and replacing the dummy gate of the gate structure with a metal gate, wherein during the replacing the dummy gate, a profile of the portion of the fin is modified. In an example, modifying the profile of the portion of the fin includes increasing a height of the portion of the fin and/or decreasing a width of the portion of the fin.Type: GrantFiled: December 4, 2012Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Hsing Hsieh, Zhiqiang Wu, Ching-Fang Huang, Jon-Hsu Ho
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Publication number: 20140138763Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device precursor. The semiconductor device precursor includes a substrate, source/drain regions on the substrate, dummy gate stacks separating the source/drain regions on the substrate and a doped region under the dummy gate stacks. The dummy gate stack is removed to form a gate trench. The doped region in the gate trench is recessed to form a channel trench. A channel layer is deposited in the channel trench to form a channel region and then a high-k (HK) dielectric layer and a metal gate (MG) are deposited on the channel region.Type: ApplicationFiled: November 16, 2012Publication date: May 22, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Chieh Yang, Wei-Hao Wu, Wen-Hsing Hsieh, Zhiqiang Wu
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Publication number: 20140138780Abstract: An embodiment fin field effect transistor (FinFET) device and method of forming the same. An embodiment method of forming a fin field effect transistor (FinFET) includes forming fins from a semiconductor substrate, forming a field oxide between the fins, forming a sacrificial gate over a channel region of the fins projecting from the field oxide, and implanting ions through the sacrificial gate to provide the channel region of the fins with a uniform doping profile.Type: ApplicationFiled: November 21, 2012Publication date: May 22, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jean-Pierre Colinge, Wen-Hsing Hsieh